When planning new IC design projects, such as SoCs or complex analog or RF chips, R&D organizations that have a firm grasp on the complexity of implementing the design wield a powerful competitive advantage. Complexity is a measure of engineering difficulty and provides the foundation for reliably estimating engineering resource requirements and development cycle time for projects, which is the essence of good project planning. Can anyone disagree that consistently reliable project plans, which means projects finish on-time and within budget, translate to higher revenue and profits? But how does one get an accurate, quantitative calculation of design complexity? [More]

You’re frustrated and suddenly stalled on the freeway and what happens in larger organizations is chillingly clear: a chain-reaction crash that creates incredible chaos across the R&D group.

Missing Schedule

Part of the reason so many semiconductor projects miss schedule is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. This is solvable problem.

Fact-based planning provides the team with data for decision-making—ensuring that projects are staffed properly to meet the demands of the design’s complexity. Estimates of design complexity, project-staffing requirements and development cycle time are generated using empirically calibrated models. This is the heart of Fact-based planning, which is used by top semiconductor companies across the industry.

Fact-based planning

• Eases the traditional tension between groups within the enterprise that struggle to communicate in different languages by guiding discussions and strategy with facts and data.
• Enables predictable revenue streams because it yields accurate schedule estimates, therefore there are no surprise shortfalls in revenue or margins.
• Leads to predictable schedules, which is crucial in an era when time to market is more important than ever, and companies can’t afford to miss the market upturn.
• Doesn’t replace bottom-up, detailed planning but complements it.

Boosting Productivity

Fact-based planning is essential to an important productivity boosting best practice: seeing the project execution pipeline clearly and managing it centrally. This best practice—and the tooling behind it—rolls up all project plans to generate a picture that shows the total resources consumed by all project plans. With this bird’s-eye view of all project plans, engineering managers can observe where there are shortfalls and over-subscriptions role by role, month by month. This becomes an essential tool for managing the pipeline.

This isn’t an airbag that protects you in a chain reaction crash. This is a radar system that prevents the crash in the first place and gets everyone to their destinations safely.

Originally published in EETimes http://www.eetimes.com/discussion/other/4205031/The-ripple-effect

By Ron Collett

From the business perspective of a semiconductor company, Numetrics’ solutions are about making substantial improvements in chip development productivity and schedule predictability. But just what is productivity, and how do you first characterize it and then improve it? What’s the outcome?

Productivity drives development throughput in your R&D organization – the higher the productivity, the greater the throughput. And throughput is a measure of how much product the engineering organization churns out during a given period of time.

There are three ways to boost R&D throughput:

• Add headcount
• Increase work-hours per week
• Raise utilization and productivity

The first two have downside: Raising R&D headcount increases cost, and more hours lead to workforce burnout and high turnover.

The only viable long-term strategies for sustaining high throughput are to increase engineering utilization and productivity.

Utilization

Increasing R&D utilization—the percentage of the engineering workforce’s effort spent on revenue-generating activities—is among the quickest and most effective ways to boost throughput. That’s because it essentially increases R&D resources without incurring additional cost.

Organizations struggling with low utilization find their engineers spend more than half their time on non-revenue-generating activities, such as sales, customer support, and product support – all of which should be handled by different groups. In large companies, that means millions of dollars a year are being squandered.

Engineering organizations in best-in-class companies, however, spend 73 percent of their engineering time on activities that generate revenue and create persistent value. By shrinking the amount of time engineers spend on projects that get cancelled, non-core research, myriad internal initiatives, and so forth, companies can significantly raise their utilization rates and, in the process, reduce R&D spending and/or develop new revenue-generating products.

Productivity

 Productivity – the second factor driving throughput – is the amount of engineering output per unit of labor expended to create that output. Productivity is a function of efficiency. Only by improving efficiency will productivity rise. Analysis of R&D efficiency compares the effort a particular set of engineering tasks should consume to what they actually consume. Reducing the effort needed to complete a set of tasks raises efficiency, which increases productivity, and this gives rise to higher throughput.

Boosting productivity requires a reliable measurement system–one yielding accurate baselines and fair comparisons. Additionally, a robust measurement system paves the way for managers to determine the absolute minimum staffing projects need to finish on time. At that point, the projects are “optimally understaffed,” which means the projects can be staffed to levels that assume the teams will meet an improved productivity level.

And there’s where best-in-class companies are pushing the productivity envelope.

Originally published in EE Times http://www.eetimes.com/discussion/other/4201131/How-productive-is-your-R-D-organization-

By Ron Collett

(Summary: As the semiconductor industry emerges from the recession, new ways of thinking are emerging as well to improve what’s becoming a new differentiator for companies: IC design development.)

All indications are the semiconductor industry is rebounding from the painful recession of the past couple of years. The latest upbeat data points include:

• Worldwide third-quarter PC microprocessor unit shipments rose 23% compared to the second quarter, reaching a new all-time high, according to market research firm International Data Corp. (IDC).
• Chip-sales growth should be 10 percent in 2010 and 8.4 percent in 2011, according to the Semiconductor Industry Association. The decline in 2009 chip sales (down 11.6 percent is now less that earlier forecast).
• Individually, companies like Marvell, TSMC and ON Semiconductor are reporting encouraging results.

But, as they say, there’s good news and bad news. The good news is obvious. The bad news is more subtle: Companies are beginning to crank up the product-development dial significantly, and this can become a challenge for R&D organizations.

As a surge of new projects occurs, hiring generally is slow to catch up to demand. This puts stress on engineering organizations. Schedules are difficult to predict, and the engineers can get shifted from one product development team to another in the race to make deadlines. Managing a portfolio of products turns into a torch-juggling exercise—spectacular to watch but done with the knowledge that the risk is high.

This is a significant problem in the fables era—a time in which IC design development is an increasingly important source of differentiation for semiconductor companies. A sudden burst of product-development activity can bring R&D organizations to their knees.

Design development productivity is something to consider as we emerge from this recession. The stakes are high, and there’s little room for error in marshalling engineering resources to get products to market quickly.

All recessions force change on business, and this one is no exception. Old ways of doing things are being replaced by new thinking on productivity—all with an eye toward making “up and to the right” last.

(Summary: For semiconductor companies, differentiation has shifted from manufacturing to improving productivity in new-product development. That realization is the easy part; getting there requires help.)

By Ron Collett

I’m always impressed with the level of optimism I find at semiconductor industry events around the world. There may be pockets of gloom about the state of the semiconductor industry, but executives certainly don’t share it. Yes, it’s not the same industry it was 10 years ago, but, no, it’s not doomed. Far from it: The dynamics are just different.

That was my message when I presented last week at Malcolm Penn’s International Electronics Forum in Geneva. Here’s why the dynamics are different:

• The industry head count has shrunk 30 percent this decade
• Industry consolidation has picked up pace
• Cost-cutting is rampant
• There’s more pressure than ever on design teams to get great products out the door on time and on budget

Here’s how the dynamics are different: Differentiation has shifted as industry disaggregation has reached an end state. There was a time when a semiconductor company differentiated itself through manufacturing and process technology (or way back when, through making its own steppers!) No longer.

So where’s the differentiation? It’s not in cost-cutting. Everyone’s doing that.

Differentiation has shifted to the heart of the semiconductor company’s value proposition: its new-product development.

Electronics Weekly’s David Manners, in his coverage of IEF last week (“What’s the Answers to the Chip Industry’s Problems? Ask IEF”), touched on how profound this can be. He quoted Alain Dutheil, CEO of ST-Ericsson, as saying 85 percent of his 8,000 employees are in R&D.

The other part of the story, which we’ve blogged about, is that most SOC projects slip schedule and most IC teams tend to underestimate their product R&D costs.

That brings me back to our IEF presentation (“Raising the Bar on Semiconductor R&D Management, Execution, and ROI”), which we created in partnership with PRTM, one of the world’s premier operational strategy consulting firms (with deep ties to the IC industry).

Our three take-aways were:

• The bar is being significantly raised on semiconductor R&D management, execution, and achieving ROI
• Companies must continuously progress through the stages of maturity to thrive (functional, project, portfolio, and cross-enterprise excellence)
• Fact-based planning is a critical foundation for ongoing NPD success

Anyone can cut costs in challenging times but winning companies find news ways to differentiate themselves, and they are the companies that come out of recessions stronger than their competition.

Summary: Re-planning a semiconductor design project is often inevitable as the program is underway. The key to effective, productive re-planning lies in understanding complexity, schedule and resources.

Change is inevitable. Economic factors, mergers and acquisitions, customer specification changes, management and strategy changes all affect project planning and execution. These factors create a need for re-planning IC projects while they are ongoing.

The key to re-planning is the same as for the original planning process: an understanding of complexity, schedule and resources. Numetrics’ NMX-ERP can capture not only the starting characteristics of your design, but also updates as work is completed. This means that at any point during the design, you can calculate the work remaining and the resource and/or schedule implications of that.

Re-planning is simply a process of updating the assumptions based on new information. From there it is a simple process to re-run the analysis, and to generate a new plan. This is easy not only because there is explicit support in the tools for re-planning and the management of multiple scenarios for a single design, but also because there is no need for data re-entry. Everything is built from the original plan, saving a great deal of time for your planners.

Schedule Risk Analyzer generates a comprehensive set of reports that quantitatively assess the underlying schedule risk, given the design’s complexity, staffing assigned to the project and target cycle-time.

The real implication of the re-planning capability is that when a change is proposed, you can quickly determine feasibility. For example, if marketing comes to you and says, “We need samples six weeks early for a key customer,” you can rapidly tell them what that means for resources. If additional resources are not available, you might consider scaling back product features to meet the new schedule. Alternatively, you may be forced to complete the design with fewer engineers than you had originally planned for. In such a case, you can quickly determine the best way to meet your business objectives with the new constraint—either reducing the feature set, or planning for a managed schedule slip.

The net benefit of Numetrics’ re-planning tools is fact-based decision-making in a time of stress. Fact-based planning improves the quality of internal decisions, leading to a healthier business and happier employees. And that can’t be bad.

Summary: Risk to IC development schedules can be minimized by comparing design plan assumptions with a database of historical industry designs and your company’s own history of completed projects to help you determine tradeoffs.

Simply put, schedule risk is the difference between the planned schedule, and the lessons of history. If you plan to finish a design with 20 engineers in 25 weeks, yet industry and corporate comparisons indicate that you need either 27 engineers or to lengthen the schedule to 34 weeks, you have identified schedule risk.

The Numetrics tools can compare your design plan assumptions with all designs in the industry database, or with a subset based on powerful filters, or most powerfully with your own company’s history of completed design projects. If your plan is more aggressive than the results achieved historically, then you risk missing your schedule. High levels of schedule risk disempower your engineers, because the plan feels unrealistic to them. It also creates business risk, especially if schedule is critical. It doesn’t make sense to agree to a plan that requires productivity much greater than you have historically been able to deliver.

On the other hand, it is reasonable to set a stretch goal that is a little better than your historical performance or the industry averages. That’s a stretch goal, and if the team believes it’s feasible, they will work hard to achieve it. This is a point where risk is managed, and the goals are achievable. Everyone likes to outperform their peers, but no one wants to be set up for failure.

By using Numetrics’ tools to analyze schedule risk, you can create a plan that is aggressive, but not so aggressive that it is doomed to fail. Such a plan is good for your team, and good for your business.

Summary: Schedule predictability is the art and science of determining the completion date for your semiconductor IC project, based on a statistical model, validated across multiple designs.

When you plan a project, you are working with incomplete information. Organizational changes, specification changes, technical challenges and more conspire to make it difficult to accurately predict when your new product will be ready.

Schedule predictability is the art and science of determining the completion date for your project, based on a statistical model, validated across multiple designs. The key ingredients are your design’s complexity, coupled with your resource plan. With these two inputs, Numetrics can significantly improve the accuracy of your schedule predictions. One customer went from consistent overruns to accuracy within a few percent on the first designs they modeled in the Numetrics toolset.

How is this possible? The core is the Numetrics ability:

• To understand which factors drive complexity
• To create a normalized characterization of your design that allows comparison with others.

When we compare your proposed design with historical productivity and schedule information, we can statistically determine the expected schedule for your new project. The accuracy of the model is enhanced by our industry database of over 1200 designs, coupled with specific information from your company’s historical project record.

The result is a robust, realistic prediction of the schedule, based on

• Complexity
• Resource availability and
• Historical data.

The value is a greatly enhanced ability to meet your market windows, time and time again.

Summary: Comparing the specifics of your semiconductor design with industry and company history enables insightful what-if scenario analysis to help manage development programs effectively .

During the planning stages for a chip design, there are a number of variables that can be tweaked in the creation of the final product plan. We can reduce or expand the feature set for a new device. We can reduce or extend the schedule. And we can reduce or increase the number of full-time-equivalent (FTE) staff allocated to the project. By manipulating these variables, we can negotiate a plan between the different stakeholders. In some cases, resources are the limiting factor. In others, the schedule is non-negotiable (for example a lot of consumer products must be ready for CES).

Running a lot of plans against all these variables has historically been difficult and time-consuming. In addition, the results have always been subject to arguments because there has been no trusted model to relate complexity, resources and schedule. Numetrics changes all that. By tweaking resource, schedule or feature set (complexity) assumptions, NMX-ERP can rapidly generate graphs that show the feasibility of each plan, and compare it with company and industry norms using their proprietary complexity engine and plan synthesizer.

The speed and defensibility of these analyses lends them great power. It is not rational to assume productivity or schedules that are significantly different from past performance, so any feasible plan must lie close to the lessons of history. There is a cost to adding features, or to shrinking the schedule, or to reducing headcount. The most effective way to negotiate these choices is with the aid of an objective toolset that combines the specifics of your design and plan with industry and company history. The tool is fast enough that you can run tens or even hundreds of plans in minutes or hours. From these scenarios you can then pick the plan that best meets your business goals.

Summary: Everybody wants to increase productivity. But there’s no free lunch: assigning too few resources to a project increases stress and creates schedule risk.

Productivity excellence is the process of maximizing productivity by setting the most aggressive targets that are still achievable. Achievable targets mean that you will meet your schedule goals. Aggressive means that everyone will be working really hard to get there. The combination ensures that your products will come to market at the earliest possible time, given hard, focused work from a team no larger than you need.

The value of productivity excellence is felt in three main areas.

• First, in these tough economic times, you can be sure you haven’t spent money on resources that are not essential to your project.
• Second, you have set the bar appropriately for an ambitious, capable engineering team.
• Third, you have controlled schedule risk, and minimized the likelihood of a schedule slip, with potentially disastrous implications for revenues and market share.

At the end of the day, productivity excellence means meeting your business goals efficiently, with a motivated workforce doing their best to meet an aggressive, but still feasible plan. Take a look at our customer case study involving Innovasic, which maximized its design throughput by benchmarking
microcontroller development team productivity.