From the business perspective of a semiconductor company, Numetrics’ solutions are about making substantial improvements in chip development productivity and schedule predictability. But just what is productivity, and how do you first characterize it and then improve it? What’s the outcome?

Productivity drives development throughput in your R&D organization – the higher the productivity, the greater the throughput. And throughput is a measure of how much product the engineering organization churns out during a given period of time.

There are three ways to boost R&D throughput:

• Add headcount
• Increase work-hours per week
• Raise utilization and productivity

The first two have downside: Raising R&D headcount increases cost, and more hours lead to workforce burnout and high turnover.

The only viable long-term strategies for sustaining high throughput are to increase engineering utilization and productivity.

Utilization

Increasing R&D utilization—the percentage of the engineering workforce’s effort spent on revenue-generating activities—is among the quickest and most effective ways to boost throughput. That’s because it essentially increases R&D resources without incurring additional cost.

Organizations struggling with low utilization find their engineers spend more than half their time on non-revenue-generating activities, such as sales, customer support, and product support – all of which should be handled by different groups. In large companies, that means millions of dollars a year are being squandered.

Engineering organizations in best-in-class companies, however, spend 73 percent of their engineering time on activities that generate revenue and create persistent value. By shrinking the amount of time engineers spend on projects that get cancelled, non-core research, myriad internal initiatives, and so forth, companies can significantly raise their utilization rates and, in the process, reduce R&D spending and/or develop new revenue-generating products.

Productivity

 Productivity – the second factor driving throughput – is the amount of engineering output per unit of labor expended to create that output. Productivity is a function of efficiency. Only by improving efficiency will productivity rise. Analysis of R&D efficiency compares the effort a particular set of engineering tasks should consume to what they actually consume. Reducing the effort needed to complete a set of tasks raises efficiency, which increases productivity, and this gives rise to higher throughput.

Boosting productivity requires a reliable measurement system–one yielding accurate baselines and fair comparisons. Additionally, a robust measurement system paves the way for managers to determine the absolute minimum staffing projects need to finish on time. At that point, the projects are “optimally understaffed,” which means the projects can be staffed to levels that assume the teams will meet an improved productivity level.

And there’s where best-in-class companies are pushing the productivity envelope.

Originally published in EE Times http://www.eetimes.com/discussion/other/4201131/How-productive-is-your-R-D-organization-

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It’s a common refrain, and I heard it this week at the IEEE VLSI Test Symposium in Santa Cruz: Moore’s Law is increasingly difficult to obey. We see evidence of this perception everywhere:

• Manufacturing costs are soaring: A fab that cost $2.5 billion to construction at 90 nm now costs $6 billion at the 22 nm node. So companies are selling off their fabs and losing what was once a huge competitive differentiation for them. Their primary differentiation is increasing their product-development capability.
• System-on-Chip (SOC) development costs run anywhere from $50 million to $100 million per project. A dwindling number of markets can support the ROI that type of investment demands.

This increasing risk has significantly cooled VC investment in our industry. In 2000, venture capitalists invested nearly $4 billion in semiconductor companies; last year, it was $771 million.

This means that to be successful in 2010 and beyond, semiconductor companies must “do Moore” with less. That requires a focus on product-development capability. How do you transform your product-development organization into a world-class team?

Here are some best practices:

• Start with an integrated framework of product-development capabilities. We, with our partners, the global operational-strategy consulting firm PRTM, counsel such a framework to improve product and cycle-time excellence. It’s remarkable how few companies have this kind of framework, but, implemented correctly, it translates into a capability to improve your overall maturity. And the more mature your product-development maturity, the faster you’ll see revenue growth.
• Optimize your R&D footprint. No one builds an SoC at a single site any more. An integrated approach to R&D management is key to taking advantage of synergies and scaling opportunities.
• Extend your enterprise: The cost of development is so high, it’s no longer possible to develop everything in house. Establishing relationships with other companies and with universities is becoming essential.

In an era of doing more with less, these best practices can help semiconductor companies “do Moore” with less, widen their competitive differentiation and increase revenues and profits.

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Sometimes the simple questions are the most vexing. That hit me this week while participating in a DesignCon panel in Santa Clara, moderated by EDN Executive Editor Ron Wilson.

The title seemed easy enough: “Getting to Design Quality Closure Without Compromising Productivity.”

But really, what IS quality? How do we define it?

My fellow panelist, Camille Kokozaki, president of Design Rivers, quipped “It’s like pornography: you know it when you see it.”

Piyush Sancheti, senior director of business development at Atrenta, came close:

“Quality is meeting the design objectives you have: whether it’s area, power, timing functionality, or, in a broader sense, customer expectations. Productivity is getting there.”

Sancheti then added:

“Being able to measure it (productivity) with tools like Numetrics is important because you want to hit your objectives as fast and effectively as possible.”

Not surprisingly, our panel wrestled with one of the big issues in design quality today: verification. It deeply affects design quality and productivity. Sancheti noted that for some teams, 70 percent of the entire design development is spent on verification.

What I see first hand from customers is they struggle to understand how verification affects their productivity. Some program managers I talk to say:

“I understand the scope of logic design and physical implementation. Verification is an unknown for me. If I give the verification team another two months, they’ll take it, but how do I know that we’re better off?”

So, I think we’re seeing that verification needs to come up with some sort of model of completion so people can move on. And that’s not easy. Our data shows that some companies toggle up the tape-outs as part of a larger verification strategy, but that can hurt overall productivity.

How we fix verification is a broader issue. Do we lean on formal methods at the architectural level as opposed to time- and engineering-consuming test vectors?

For now, our role is to help teams quantify their design effort, properly staff their projects, and understand where they stand with respect to the industry’s best teams. From there they can make fact-based decisions to drive productivity improvements.

That’s our contribution to the broader challenges of verification and design quality, but as we all know, it takes a village (and many future industry panels) to come up with the solution.

(Jeff is Numetrics’ director of professional services and product marketing).

Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

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By Ron Collett

The latest venture capital investment figures are out from PricewaterhouseCoopers’ MoneyTree and the National Venture Capital Association (NVCA). They’re not pretty.

VCs spent just $17.7 billion on 2,795 deals last year. That’s down 36 percent from $27.9 billion in 2008, and it represents the lowest dollar amount and number of investments since 1997.

The chart I pulled together above, based on that data, shows the quarterly VC investment trends for semiconductor companies in just the past three years. Not an encouraging trend line. Total VC investment last year in our industry was $771 million, compared with a peak of $3.4 billion in 2000. What a difference a decade makes.

This realignment of dollars has brought about new expectations from investors and from semiconductor vendors.

Speaking to The Wall Street Journal last week, Bob Ackerman, a venture capitalist at Allegis Capital in Palo Alto, said:

We’re preoccupied by capital efficiency.

Those two words, “capital efficiency,” speak directly to the semiconductor industry’s challenge. This focus on capital efficiency is why semiconductor vendors should be increasingly preoccupied with boosting engineering productivity to get the most from their R&D budget. Lacking an internal fab for differentiation in the fabless era, companies are looking for new ways to gain competitive advantage, and they’re training their sights on their R&D organizations.

The industry’s best-in-class semiconductor IDMs in fact have jumped on this imperative, especially as many of them have shed the last of their owned fabs and now need to compete with fabless companies.

But it works the other way too: Long-time fabless players suddenly find big new competitors that have shed their fabs. They too are looking to boost product-development productivity to stay one step ahead of their new competition.

It’s clear the days of big-time investment are a thing of the past. Today, good companies are those with innovative product ideas; great companies are those that also drive highly productive R&D organizations to get those products completed on predictable schedules and to market ahead of the competition to realize higher returns.

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Summary: Re-planning a semiconductor design project is often inevitable as the program is underway. The key to effective, productive re-planning lies in understanding complexity, schedule and resources.

Change is inevitable. Economic factors, mergers and acquisitions, customer specification changes, management and strategy changes all affect project planning and execution. These factors create a need for re-planning IC projects while they are ongoing.

The key to re-planning is the same as for the original planning process: an understanding of complexity, schedule and resources. Numetrics’ NMX-ERP can capture not only the starting characteristics of your design, but also updates as work is completed. This means that at any point during the design, you can calculate the work remaining and the resource and/or schedule implications of that.

Re-planning is simply a process of updating the assumptions based on new information. From there it is a simple process to re-run the analysis, and to generate a new plan. This is easy not only because there is explicit support in the tools for re-planning and the management of multiple scenarios for a single design, but also because there is no need for data re-entry. Everything is built from the original plan, saving a great deal of time for your planners.

Schedule Risk Analyzer generates a comprehensive set of reports that quantitatively assess the underlying schedule risk, given the design’s complexity, staffing assigned to the project and target cycle-time.

The real implication of the re-planning capability is that when a change is proposed, you can quickly determine feasibility. For example, if marketing comes to you and says, “We need samples six weeks early for a key customer,” you can rapidly tell them what that means for resources. If additional resources are not available, you might consider scaling back product features to meet the new schedule. Alternatively, you may be forced to complete the design with fewer engineers than you had originally planned for. In such a case, you can quickly determine the best way to meet your business objectives with the new constraint—either reducing the feature set, or planning for a managed schedule slip.

The net benefit of Numetrics’ re-planning tools is fact-based decision-making in a time of stress. Fact-based planning improves the quality of internal decisions, leading to a healthier business and happier employees. And that can’t be bad.

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But how does a semiconductor design team approach the challenge when its size is limited by a fixed budget and the delivery date was set in stone? Infineon engaged with Numetrics to tackle the design challenge, and it ended up achieving 20 percent higher productivity than other projects. Read this case study to learn how Numetrics’ software and methodology helped Infineon gets its DECT project to market.

The case study is among several you can find here on the Numetrics site.

Does the Infineon experience resonate with you?

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Summary: Everybody wants to increase productivity. But there’s no free lunch: assigning too few resources to a project increases stress and creates schedule risk.

Productivity excellence is the process of maximizing productivity by setting the most aggressive targets that are still achievable. Achievable targets mean that you will meet your schedule goals. Aggressive means that everyone will be working really hard to get there. The combination ensures that your products will come to market at the earliest possible time, given hard, focused work from a team no larger than you need.

The value of productivity excellence is felt in three main areas.

• First, in these tough economic times, you can be sure you haven’t spent money on resources that are not essential to your project.
• Second, you have set the bar appropriately for an ambitious, capable engineering team.
• Third, you have controlled schedule risk, and minimized the likelihood of a schedule slip, with potentially disastrous implications for revenues and market share.

At the end of the day, productivity excellence means meeting your business goals efficiently, with a motivated workforce doing their best to meet an aggressive, but still feasible plan. Take a look at our customer case study involving Innovasic, which maximized its design throughput by benchmarking
microcontroller development team productivity.

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Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

• We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.

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