By Ron Collett

The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

Here’s a sampling of the presentations:

• “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
• “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
• “Energy Efficient Design at 65nm – What Really Works!”

And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

Wrong.

Projects slip for a number of reasons:

• We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
• We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
• Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

Typical bottom-up reactions to managing such complexity tend to fall into two categories:

• Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
• Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

• Quantified estimates of the chip’s complexity
• The team’s productivity
• A model of the rate at which effort will be expended on the project.

With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

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By Ron Collett

For the semiconductor industry, there not only is change in the air, there’s thoughtful debate about just what that change looks like.

I’ve been mulling over a couple of intriguing posts, one by another newly minted industry blogger, Sanjay Srivastava, CEO of Denali, and the other on EDN by Kaben Wireless Silicon CEO Paul Slaby.

In Sanjay’s blog, Conversation on Innovation, he’s been mulling how fabless semiconductor startups can survive in the current climate.

He argues (in Funding Fabless Semiconductor Startups) that solutions need to look at how and where money is invested, how we “stage” investments (i.e. valuing investments in IP differently than in silicon) and how we address software investment:

I believe if we get creative about the current fabless investment model, not every semiconductor opportunity needs to be a billion-dollar opportunity before it can attract meaningful investment.

In his EDN post and in a separate webcast, Slaby argues for a “semi-fabless” model:

The semi-fabless company is essentially a combination of an IP provider, a design house, and an outsourced R&D operation. Its core competence and strength lies in specialized R&D and product development capabilities whereas it outsources product delivery operations to the ‘old’ fabless company with the entire infrastructure and the pipeline to market already in place.

There’s no doubt the investment formula needs to be reconsidered. For a semiconductor company to break even, it needs $40-$100 million and six to eight years. More troubling, however, is the selling price of semiconductor startups has been steadily declining. In 2007 it was $160 million; in 2008 it was $95 million and in 2009 the average has been $65 million, according to an EE Times story referencing Lip-Bu Tan, chairman of Walden International, and now CEO of Cadence.

The good thing is there are a lot of “smartest guys in the room” in this industry, and collectively we’re shaping the industry’s future in three main ways:

• Companies are differentiating on products

• Executives, such as Sanjay and Paul and others, are helping drive the investment conversation

• And companies like ours are illuminating the differentiation and benefits of focusing on product-development productivity—fabless companies’ key differentiator today—and overall portfolio management.

This new differentiation is key; it’s key to how companies grow and gain market share and it’s key to the industry’s future.

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The phrase “top gun” generally refers to hot-shot fighter pilots performing amazing feats high in the sky, but increasingly it’s being used to describe great engineering managers doing amazing things on land. Numetrics has put together an online seminar covering the best practices of leading IC project planners.

The webinar describes eight techniques used by top-gun engineering managers, followed by a demonstration of Numetrics’ NMX-ERP™ solution and IC Industry Database containing more than 1400 completed IC designs from multiple industry segments.

The webinar presented the following best practices:

1. Computing IC complexity statistically
2. Estimation of resource requirements based on models
3. Rigorous “what-if” analysis for schedule / resource optimization
4. Benchmarking project execution assumptions
5. Determining the most aggressive, yet achievable project plan
6. Quantitatively assessing the schedule / resource implications of each feature request
7. Performing root-cause analysis at the project close milestone
8. Foreseeing resource shortfalls across the project pipeline.

The demonstration showed a live application of the Numetrics toolset, through a realistic scenario involving balancing IC specification and resource availability in the context of a fixed schedule.

You may view the webinar at http://techonline.stream57.com/numetrics/.

For more information, please e-mail info@numetrics.com

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Summary: Schedule predictability is the art and science of determining the completion date for your semiconductor IC project, based on a statistical model, validated across multiple designs.

When you plan a project, you are working with incomplete information. Organizational changes, specification changes, technical challenges and more conspire to make it difficult to accurately predict when your new product will be ready.

Schedule predictability is the art and science of determining the completion date for your project, based on a statistical model, validated across multiple designs. The key ingredients are your design’s complexity, coupled with your resource plan. With these two inputs, Numetrics can significantly improve the accuracy of your schedule predictions. One customer went from consistent overruns to accuracy within a few percent on the first designs they modeled in the Numetrics toolset.

How is this possible? The core is the Numetrics ability:

• To understand which factors drive complexity
• To create a normalized characterization of your design that allows comparison with others.

When we compare your proposed design with historical productivity and schedule information, we can statistically determine the expected schedule for your new project. The accuracy of the model is enhanced by our industry database of over 1200 designs, coupled with specific information from your company’s historical project record.

The result is a robust, realistic prediction of the schedule, based on

• Complexity
• Resource availability and
• Historical data.

The value is a greatly enhanced ability to meet your market windows, time and time again.

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Summary: Comparing the specifics of your semiconductor design with industry and company history enables insightful what-if scenario analysis to help manage development programs effectively .

During the planning stages for a chip design, there are a number of variables that can be tweaked in the creation of the final product plan. We can reduce or expand the feature set for a new device. We can reduce or extend the schedule. And we can reduce or increase the number of full-time-equivalent (FTE) staff allocated to the project. By manipulating these variables, we can negotiate a plan between the different stakeholders. In some cases, resources are the limiting factor. In others, the schedule is non-negotiable (for example a lot of consumer products must be ready for CES).

Running a lot of plans against all these variables has historically been difficult and time-consuming. In addition, the results have always been subject to arguments because there has been no trusted model to relate complexity, resources and schedule. Numetrics changes all that. By tweaking resource, schedule or feature set (complexity) assumptions, NMX-ERP can rapidly generate graphs that show the feasibility of each plan, and compare it with company and industry norms using their proprietary complexity engine and plan synthesizer.

The speed and defensibility of these analyses lends them great power. It is not rational to assume productivity or schedules that are significantly different from past performance, so any feasible plan must lie close to the lessons of history. There is a cost to adding features, or to shrinking the schedule, or to reducing headcount. The most effective way to negotiate these choices is with the aid of an objective toolset that combines the specifics of your design and plan with industry and company history. The tool is fast enough that you can run tens or even hundreds of plans in minutes or hours. From these scenarios you can then pick the plan that best meets your business goals.

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Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

• We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.

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Summary: Design complexity can be quantified and communicated in a way that makes IC projects predictable and more productive.

It doesn’t take a rocket scientist to know that the resources and time required to build a chip vary from one design to another. The variation is a function of how difficult the chip will be to build. We measure that and call it complexity.

The hard part, however, is to know which attributes of the design correlate to the effort required to build the chip.

• Is clock speed important?
• What about the number of transistors?
• Re-use?
• Analog and mixed signal?
• Voltage islands?
• Modes?

The list goes on and on. One of the reasons why the NMX-ERP™ software suite accurately forecasts the time and resource requirements for a design is that our engineers, using more than a thousand design projects, have developed a deep understanding of just how hard a given project may be so your engineers can be more productive.

Knowing how to translate chip-design attributes into complexity is the foundation of apples-to-apples comparisons between designs. That’s critical to making sure your latest design can be compared with other industry designs, as well as designs your company has done in the past. After taking in all the complexity factors as chip specifications, Numetrics’ engines can reliably and rapidly calculate the relative complexity of your design, as compared with every other design in our industry database. That’s the foundation upon which all the plan synthesis, what-if scenario analysis, re-planning and root-cause analysis capabilities of NMX-ERP are built.

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