By Ron Collett

The concept seems simple: The more ip blocks you re-use in an IC or system design, the faster and more productively you’ll get your design done. The ITRS roadmap began identifying the benefits as long ago as 1997, showing the industry could reasonably expect 56,000 gates per designer per year when using large ip blocks (75,000-1 million gates). By 2007 that figure was up to 600,000 gates per designer per year, a tenfold increase.

There’s no doubt design reuse is here to stay. In 2007, a third of all logic was reused design blocks. That’s expected to rise to nearly 50 percent by 2015, according to the ITRS.

The numbers and the theory behind it are encouraging, but reality is much different. Making 30 percent of your design from reused IP blocks doesn’t mean you’re going to be 30 percent more productive at the end of the project. That’s because IC design teams tend to underestimate the work needed to implement the reused IP. This can cause project delays and missed market opportunities.

The challenge is that it’s very difficult to estimate design complexity, especially the impact of reuse. IC design schedules can falter because of the inability to estimate the impact of IP modifications on project effort.

Even a small percentage of reuse can add outsized effort to a development project. For example, if you add one new block of 600,000 gates to a 6 million-gate design, you’re adding 10 percent to the IC but increasing the effort required on the project by 24 percent. Adding 10 percent new circuitry to all blocks in that 6 million-gate design—with 90 percent of each block being re-used—doubles the effort required on the project, even though it increases the IC size by just 10 percent to 6.6 million gates.

This issue will be part of a larger discussion Dec. 1 at IP-ESC 2009 in Grenoble. We were invited to sit on a panel—“IP Reuse vs. IP Leverage: What’s the difference, and what are the issues?”—with Kathryn Kranen, CEO of Jasper Design Automation, and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics. Our director of professional services, Andrea Fortunato, will represent Numetrics.

This is a well-timed panel in my opinion because re-use is an issue that transcends the industry and is crucial for its future. And how we go about optimizing design re-use is crucial to manage today.

By Ron Collett

(Summary: As the semiconductor industry emerges from the recession, new ways of thinking are emerging as well to improve what’s becoming a new differentiator for companies: IC design development.)

All indications are the semiconductor industry is rebounding from the painful recession of the past couple of years. The latest upbeat data points include:

• Worldwide third-quarter PC microprocessor unit shipments rose 23% compared to the second quarter, reaching a new all-time high, according to market research firm International Data Corp. (IDC).
• Chip-sales growth should be 10 percent in 2010 and 8.4 percent in 2011, according to the Semiconductor Industry Association. The decline in 2009 chip sales (down 11.6 percent is now less that earlier forecast).
• Individually, companies like Marvell, TSMC and ON Semiconductor are reporting encouraging results.

But, as they say, there’s good news and bad news. The good news is obvious. The bad news is more subtle: Companies are beginning to crank up the product-development dial significantly, and this can become a challenge for R&D organizations.

As a surge of new projects occurs, hiring generally is slow to catch up to demand. This puts stress on engineering organizations. Schedules are difficult to predict, and the engineers can get shifted from one product development team to another in the race to make deadlines. Managing a portfolio of products turns into a torch-juggling exercise—spectacular to watch but done with the knowledge that the risk is high.

This is a significant problem in the fables era—a time in which IC design development is an increasingly important source of differentiation for semiconductor companies. A sudden burst of product-development activity can bring R&D organizations to their knees.

Design development productivity is something to consider as we emerge from this recession. The stakes are high, and there’s little room for error in marshalling engineering resources to get products to market quickly.

All recessions force change on business, and this one is no exception. Old ways of doing things are being replaced by new thinking on productivity—all with an eye toward making “up and to the right” last.

Getting back into any market after a few years’ absence is a challenge, especially when it’s the hyper-competitive, high-volume, low-margin consumer market. But Infineon, which had years of experience selling Digital Enhanced Cordless Telecommunications (DECT) chipsets into that space saw opportunity to re-assert itself in the global market.

But how does a semiconductor design team approach the challenge when its size is limited by a fixed budget and the delivery date was set in stone? Infineon engaged with Numetrics to tackle the design challenge, and it ended up achieving 20 percent higher productivity than other projects. Read this case study to learn how Numetrics’ software and methodology helped Infineon gets its DECT project to market.

The case study is among several you can find here on the Numetrics site.

Does the Infineon experience resonate with you?

Summary: Everybody wants to increase productivity. But there’s no free lunch: assigning too few resources to a project increases stress and creates schedule risk.

Productivity excellence is the process of maximizing productivity by setting the most aggressive targets that are still achievable. Achievable targets mean that you will meet your schedule goals. Aggressive means that everyone will be working really hard to get there. The combination ensures that your products will come to market at the earliest possible time, given hard, focused work from a team no larger than you need.

The value of productivity excellence is felt in three main areas.

• First, in these tough economic times, you can be sure you haven’t spent money on resources that are not essential to your project.
• Second, you have set the bar appropriately for an ambitious, capable engineering team.
• Third, you have controlled schedule risk, and minimized the likelihood of a schedule slip, with potentially disastrous implications for revenues and market share.

At the end of the day, productivity excellence means meeting your business goals efficiently, with a motivated workforce doing their best to meet an aggressive, but still feasible plan. Take a look at our customer case study involving Innovasic, which maximized its design throughput by benchmarking
microcontroller development team productivity.

Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

• We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.