By Ron Collett

From the business perspective of a semiconductor company, Numetrics’ solutions are about making substantial improvements in chip development productivity and schedule predictability. But just what is productivity, and how do you first characterize it and then improve it? What’s the outcome?

Productivity drives development throughput in your R&D organization – the higher the productivity, the greater the throughput. And throughput is a measure of how much product the engineering organization churns out during a given period of time.

There are three ways to boost R&D throughput:

• Add headcount
• Increase work-hours per week
• Raise utilization and productivity

The first two have downside: Raising R&D headcount increases cost, and more hours lead to workforce burnout and high turnover.

The only viable long-term strategies for sustaining high throughput are to increase engineering utilization and productivity.

Utilization

Increasing R&D utilization—the percentage of the engineering workforce’s effort spent on revenue-generating activities—is among the quickest and most effective ways to boost throughput. That’s because it essentially increases R&D resources without incurring additional cost.

Organizations struggling with low utilization find their engineers spend more than half their time on non-revenue-generating activities, such as sales, customer support, and product support – all of which should be handled by different groups. In large companies, that means millions of dollars a year are being squandered.

Engineering organizations in best-in-class companies, however, spend 73 percent of their engineering time on activities that generate revenue and create persistent value. By shrinking the amount of time engineers spend on projects that get cancelled, non-core research, myriad internal initiatives, and so forth, companies can significantly raise their utilization rates and, in the process, reduce R&D spending and/or develop new revenue-generating products.

Productivity

 Productivity – the second factor driving throughput – is the amount of engineering output per unit of labor expended to create that output. Productivity is a function of efficiency. Only by improving efficiency will productivity rise. Analysis of R&D efficiency compares the effort a particular set of engineering tasks should consume to what they actually consume. Reducing the effort needed to complete a set of tasks raises efficiency, which increases productivity, and this gives rise to higher throughput.

Boosting productivity requires a reliable measurement system–one yielding accurate baselines and fair comparisons. Additionally, a robust measurement system paves the way for managers to determine the absolute minimum staffing projects need to finish on time. At that point, the projects are “optimally understaffed,” which means the projects can be staffed to levels that assume the teams will meet an improved productivity level.

And there’s where best-in-class companies are pushing the productivity envelope.

Originally published in EE Times http://www.eetimes.com/discussion/other/4201131/How-productive-is-your-R-D-organization-

By Jeffrey Eversmann
After two years of doom and gloom, it’s refreshing to attend an industry event and hear talk of innovation—at all levels. That was the atmosphere at a recent GSA Silicon Series luncheon I attended in Austin, Texas, that featured a panel discussion on blurring technology lines.

At the application-segment level, Patrick Moorhead, marketing vice president with AMD, joked:

“I’ve been hearing that the desktop market is dying for the past 15 years.”

He made that quip after holding up the “4th screen” examples he had brought with him: an iPad and a Sony eBook reader. “Only 5-10% of consumers back up their data, so a fixed device will always be in the home,” Moorhead said.

I agree. While I like the professional security that a proliferation of leading-edge microprocessors brings, I am burdened by the yearly upgrade rotation I am now on to keep current the six-plus PCs in my home. All of us in the semiconductor industry have been through multiple iterations of the tablet device, some of them from Apple. As was often said by the panel, “it’s not an either-or these days.”

Fellow panelist Naveed Sherwani, CEO of Open-Silicon, Inc., added “the new form factor will succeed if it is useful.” So, panelists agreed that the iPad is not a desktop (or even laptop) killer. The question is: Will the average consumer add yet another device to the list of electronic gadgets we carry around each day?

The panel shifted to the technology level and wrestled with an intriguing question: Will ARM replace x86 in the desktop or will x86 replace ARM in the SoC market? While some in the audience checked email on their smartphones, Sandeep Shah, director of marketing and applications at Marvell Semiconductor, Inc., and Sherwani tackled the question.

Shah argued that an “ARM architecture licensee can bring together the best of both worlds.” (This is a very interesting perspective in light of Apple’s recent purchase of Intrinsity, which worked with Samsung to develop the ARM Cortex-based A4 processor.)

Shifting processor sands

Sherwani was quick to add that while there really hasn’t been an attempt by x86 to take over SoC design, that doesn’t mean an attempt isn’t brewing:

“In the next three years or so, things will get more competitive and more intense, when x86 is available for SoC development.”

Then it was time to move on to another much-discussed technology challenge, low power design. The panel members pulled out their different battery-powered devices and rattled off the actual vs. published battery life. “What we really need is more disclosure, a ‘truth-in-battery-life’ from silicon providers,” Moorhead said.

Shah, who probably lives power issues on a daily basis, talked about how the different Blackberry models used different chips from Marvell to get different power performance in the system. Marvell focuses on both system-level and gate-level approaches to power management. Sherwani wrapped things up from a design perspective saying “we have just scratched the surface on lower power design.” Maybe what we need is a Moore’s Law for low power design – something that will challenge engineers to do things that today are viewed as impossible.

All in all, the GSA luncheon was a great opportunity to re-connect with fellow semiconductor engineers. We exchanged cards with the same cell phone numbers, but with new company names, new titles, and new addresses. We talked about how tough things have been but how happy we are to be traveling less and spending more time with our families.

It felt like the calm before the innovation storm. I don’t know about you, but I’m here and getting ready for it.

By Ron Collett

It’s a common refrain, and I heard it this week at the IEEE VLSI Test Symposium in Santa Cruz: Moore’s Law is increasingly difficult to obey. We see evidence of this perception everywhere:

• Manufacturing costs are soaring: A fab that cost $2.5 billion to construction at 90 nm now costs $6 billion at the 22 nm node. So companies are selling off their fabs and losing what was once a huge competitive differentiation for them. Their primary differentiation is increasing their product-development capability.
• System-on-Chip (SOC) development costs run anywhere from $50 million to $100 million per project. A dwindling number of markets can support the ROI that type of investment demands.

This increasing risk has significantly cooled VC investment in our industry. In 2000, venture capitalists invested nearly $4 billion in semiconductor companies; last year, it was $771 million.

This means that to be successful in 2010 and beyond, semiconductor companies must “do Moore” with less. That requires a focus on product-development capability. How do you transform your product-development organization into a world-class team?

Here are some best practices:

• Start with an integrated framework of product-development capabilities. We, with our partners, the global operational-strategy consulting firm PRTM, counsel such a framework to improve product and cycle-time excellence. It’s remarkable how few companies have this kind of framework, but, implemented correctly, it translates into a capability to improve your overall maturity. And the more mature your product-development maturity, the faster you’ll see revenue growth.
• Optimize your R&D footprint. No one builds an SoC at a single site any more. An integrated approach to R&D management is key to taking advantage of synergies and scaling opportunities.
• Extend your enterprise: The cost of development is so high, it’s no longer possible to develop everything in house. Establishing relationships with other companies and with universities is becoming essential.

In an era of doing more with less, these best practices can help semiconductor companies “do Moore” with less, widen their competitive differentiation and increase revenues and profits.

By Ron Collett

We’re gearing up for DVCon (Feb. 22-25) in San Jose and not just because we’re participating in a panel. DVCon (on Twitter, @dvCon), which has emerged as a increasingly important event in recent years, features as keynoter Cadence CEO Lip-bu Tan. His topic gives a new voice to the mounting productivity crisis in semiconductor and system design.

According to an abstract of his talk:

“…the industry must approach the product development process much differently. The classic ‘brute force’ methods cannot scale to support the complexity of today’s SoCs and Systems. These traditional methods result in mounting costs and unpredictable schedules that are detrimental to profitability.”

• Cadence approaches the problem by giving engineers (among many other things) design exploration options that speed the implementation of the physical architecture of a chip.

• Numetrics approaches the problem by helping teams quantify the complexity of their design effort and build reliable project and staffing plans. This is crucial in an era where most IC projects slip schedule significantly.

Our vice president of professional services, Steve Gary, will speak on a panel just after Tan’s, titled “What Keeps You Up at Night?” It’s moderated by JL Gray from Verilabs, who writes the excellent Cool Verification blog; he’s posted a panel preview this week.  Also in the conversation will be John Goodenough from ARM Ltd., Sheela Pillai of Advanced Micro Devices, Inc., Jim Crocker from Paradigm Works, Inc. and Victor Melamed from Ambarella.

There are plenty of things keeping the industry up at night, but I think we’ll hear a lot of excellent ways to overcome the sleeplessness and drive productivity—and the industry—to the next level. Hope to see you there.

(Summary: The recently published book “The Checklist Manifesto” holds important lessons for how semiconductor and embedded systems design teams can improve their product-development productivity.)

“The complexity of what we have to deliver on exceeds our abilities as experts partly because the volume of knowledge has exceeded what training can possible provide an expert.”

By Ron Collett

That’s how Atul Gawande, author of “The Checklist Manifesto,” sets up the problem during a podcast interview with Harvard IdeaCast. Gawande is a surgeon and a staff writer for The New Yorker magazine who looks at our ability to be productive in complex situations. His interest, of course, is improving surgical outcomes.
There are, he says, 6,000 drugs and 4,000 medical procedures and increasingly specialized doctors and nurses. We’ve all read stories where surgical implements get left behind in the patient’s body.

I was fascinated by how relevant this is to semiconductor and embedded design. Teams of varying sizes are pulled together on a regular basis—digital specialists, memory specialists, analog designers, software engineers. They’re asked to build increasingly complex systems, with tighter market opportunities, and, like surgery, they find it nearly impossible to plan for the unexpected.

Process, not check marks

Gawande’s checklist approach isn’t about ticking off boxes per se. In the operating room, Gawande devised a two-minute checklist that builds in pauses during surgery to make sure that tasks have been accomplished, that blood is still on hand, and so forth. Perhaps most astonishingly, before the first incision is made, the team takes time to introduce each other by name, so everyone knows everyone else and their expertise and the goal of the operation.

He cites a study done by Geoffrey Smart, who studied decision making among venture capitalists. He compared outcomes of those VCs who, in choosing a entrepreneur, went with their gut (the “art critics”) and those who employed a checklist approach in their selection process (the “airline captains”).

Those who used the checklist approach had far fewer regrets about their selection of managers, and their investments had higher returns.

But the vast majority of VCs are “art critics,” relying on their instincts and experience, rather than the more successful approach.

In system design, many managers rely on their instincts at the beginning of product development to assess how much staff they’ll need and how long the project will take. Clearly something’s wrong because more than 80 percent of semiconductor projects slip schedule.

Learning from the past

It doesn’t have to be this way. Gawande points out that some in the investment banking community rigorously study past investments to understand where failed investments went awry. Sometimes that education leads to adding a check for their next investment checklist: “read all foot notes in the prospectus,” for example.

Successful system-design teams, whether in name or spirit, use similar approaches, and they start with benchmarking themselves against the industry or their own past efforts to understand how to approach their latest product development.

As Gawande implies, it’s often the simplest approaches—and, I’d add, approaches based on facts rather than instinct—that work most effectively.

By Jeff Eversmann

Sometimes the simple questions are the most vexing. That hit me this week while participating in a DesignCon panel in Santa Clara, moderated by EDN Executive Editor Ron Wilson.

The title seemed easy enough: “Getting to Design Quality Closure Without Compromising Productivity.”

But really, what IS quality? How do we define it?

My fellow panelist, Camille Kokozaki, president of Design Rivers, quipped “It’s like pornography: you know it when you see it.”

Piyush Sancheti, senior director of business development at Atrenta, came close:

“Quality is meeting the design objectives you have: whether it’s area, power, timing functionality, or, in a broader sense, customer expectations. Productivity is getting there.”

Sancheti then added:

“Being able to measure it (productivity) with tools like Numetrics is important because you want to hit your objectives as fast and effectively as possible.”

Not surprisingly, our panel wrestled with one of the big issues in design quality today: verification. It deeply affects design quality and productivity. Sancheti noted that for some teams, 70 percent of the entire design development is spent on verification.

What I see first hand from customers is they struggle to understand how verification affects their productivity. Some program managers I talk to say:

“I understand the scope of logic design and physical implementation. Verification is an unknown for me. If I give the verification team another two months, they’ll take it, but how do I know that we’re better off?”

So, I think we’re seeing that verification needs to come up with some sort of model of completion so people can move on. And that’s not easy. Our data shows that some companies toggle up the tape-outs as part of a larger verification strategy, but that can hurt overall productivity.

How we fix verification is a broader issue. Do we lean on formal methods at the architectural level as opposed to time- and engineering-consuming test vectors?

For now, our role is to help teams quantify their design effort, properly staff their projects, and understand where they stand with respect to the industry’s best teams. From there they can make fact-based decisions to drive productivity improvements.

That’s our contribution to the broader challenges of verification and design quality, but as we all know, it takes a village (and many future industry panels) to come up with the solution.

(Jeff is Numetrics’ director of professional services and product marketing).

Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

By Ron Collett

The latest venture capital investment figures are out from PricewaterhouseCoopers’ MoneyTree and the National Venture Capital Association (NVCA). They’re not pretty.

VCs spent just $17.7 billion on 2,795 deals last year. That’s down 36 percent from $27.9 billion in 2008, and it represents the lowest dollar amount and number of investments since 1997.

The chart I pulled together above, based on that data, shows the quarterly VC investment trends for semiconductor companies in just the past three years. Not an encouraging trend line. Total VC investment last year in our industry was $771 million, compared with a peak of $3.4 billion in 2000. What a difference a decade makes.

This realignment of dollars has brought about new expectations from investors and from semiconductor vendors.

Speaking to The Wall Street Journal last week, Bob Ackerman, a venture capitalist at Allegis Capital in Palo Alto, said:

We’re preoccupied by capital efficiency.

Those two words, “capital efficiency,” speak directly to the semiconductor industry’s challenge. This focus on capital efficiency is why semiconductor vendors should be increasingly preoccupied with boosting engineering productivity to get the most from their R&D budget. Lacking an internal fab for differentiation in the fabless era, companies are looking for new ways to gain competitive advantage, and they’re training their sights on their R&D organizations.

The industry’s best-in-class semiconductor IDMs in fact have jumped on this imperative, especially as many of them have shed the last of their owned fabs and now need to compete with fabless companies.

But it works the other way too: Long-time fabless players suddenly find big new competitors that have shed their fabs. They too are looking to boost product-development productivity to stay one step ahead of their new competition.

It’s clear the days of big-time investment are a thing of the past. Today, good companies are those with innovative product ideas; great companies are those that also drive highly productive R&D organizations to get those products completed on predictable schedules and to market ahead of the competition to realize higher returns.

By Ron Collett

The concept seems simple: The more ip blocks you re-use in an IC or system design, the faster and more productively you’ll get your design done. The ITRS roadmap began identifying the benefits as long ago as 1997, showing the industry could reasonably expect 56,000 gates per designer per year when using large ip blocks (75,000-1 million gates). By 2007 that figure was up to 600,000 gates per designer per year, a tenfold increase.

There’s no doubt design reuse is here to stay. In 2007, a third of all logic was reused design blocks. That’s expected to rise to nearly 50 percent by 2015, according to the ITRS.

The numbers and the theory behind it are encouraging, but reality is much different. Making 30 percent of your design from reused IP blocks doesn’t mean you’re going to be 30 percent more productive at the end of the project. That’s because IC design teams tend to underestimate the work needed to implement the reused IP. This can cause project delays and missed market opportunities.

The challenge is that it’s very difficult to estimate design complexity, especially the impact of reuse. IC design schedules can falter because of the inability to estimate the impact of IP modifications on project effort.

Even a small percentage of reuse can add outsized effort to a development project. For example, if you add one new block of 600,000 gates to a 6 million-gate design, you’re adding 10 percent to the IC but increasing the effort required on the project by 24 percent. Adding 10 percent new circuitry to all blocks in that 6 million-gate design—with 90 percent of each block being re-used—doubles the effort required on the project, even though it increases the IC size by just 10 percent to 6.6 million gates.

This issue will be part of a larger discussion Dec. 1 at IP-ESC 2009 in Grenoble. We were invited to sit on a panel—“IP Reuse vs. IP Leverage: What’s the difference, and what are the issues?”—with Kathryn Kranen, CEO of Jasper Design Automation, and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics. Our director of professional services, Andrea Fortunato, will represent Numetrics.

This is a well-timed panel in my opinion because re-use is an issue that transcends the industry and is crucial for its future. And how we go about optimizing design re-use is crucial to manage today.

By Ron Collett

(Summary: As the semiconductor industry emerges from the recession, new ways of thinking are emerging as well to improve what’s becoming a new differentiator for companies: IC design development.)

All indications are the semiconductor industry is rebounding from the painful recession of the past couple of years. The latest upbeat data points include:

• Worldwide third-quarter PC microprocessor unit shipments rose 23% compared to the second quarter, reaching a new all-time high, according to market research firm International Data Corp. (IDC).
• Chip-sales growth should be 10 percent in 2010 and 8.4 percent in 2011, according to the Semiconductor Industry Association. The decline in 2009 chip sales (down 11.6 percent is now less that earlier forecast).
• Individually, companies like Marvell, TSMC and ON Semiconductor are reporting encouraging results.

But, as they say, there’s good news and bad news. The good news is obvious. The bad news is more subtle: Companies are beginning to crank up the product-development dial significantly, and this can become a challenge for R&D organizations.

As a surge of new projects occurs, hiring generally is slow to catch up to demand. This puts stress on engineering organizations. Schedules are difficult to predict, and the engineers can get shifted from one product development team to another in the race to make deadlines. Managing a portfolio of products turns into a torch-juggling exercise—spectacular to watch but done with the knowledge that the risk is high.

This is a significant problem in the fables era—a time in which IC design development is an increasingly important source of differentiation for semiconductor companies. A sudden burst of product-development activity can bring R&D organizations to their knees.

Design development productivity is something to consider as we emerge from this recession. The stakes are high, and there’s little room for error in marshalling engineering resources to get products to market quickly.

All recessions force change on business, and this one is no exception. Old ways of doing things are being replaced by new thinking on productivity—all with an eye toward making “up and to the right” last.

By Alex Silbey

(Summary: We inevitably get questions about Numetrics’ technology after webinars or live event presentations, and we’d like to share some of them in the spirit of helping you understand more about our products and solutions. Here are answers to several recent questions in the virtual mail bag).

Q: How do you define productivity?

A: We calculate complexity of the project and we divide the complexity units by total number of person weeks required to get that product out to volume production. That quotient gives you the productivity number. The typical range is 500 on the low end for a large team to 3000 for a small team.

There’s another measure, which is throughput, and throughput is complexity units per week. That’s a measure of normalized cycle team. Productivity is efficiency of the team and higher number is better.

Q: I’ve heard that in some sectors productivity decreases as team size increases. Is this true in semiconductor product development?

A: It’s a universal effect across pretty much any activity that has to do with building things. When you build larger teams, each person is doing a smaller and smaller slice of the overall work. More work has to be split apart and then put back together. Bigger teams equal more meetings and more management required. It’s universal and it’s inevitable. With the Numetrics approach, you can minimize this effect—decreasing productivity curve is flatter than it would otherwise be.

Q: It’s impossible to predict in a design project how many times customer requirements will change, when your EDA tools go buggy or if a key contributor leaves the team. So how do you quantify schedule risk with so many unpredictable variables?

A: The simple answer is our tools don’t predict things. You have a draw a line between statistical analysis and a crystal ball.

What Numetrics’ tools do is take your inputs of design parameters and measure them against the history of more than 1,500 design projects over eight generations of technology evolution (here’s a link to a demo of our tools). Using the data from those hundreds and hundreds of designs, this builds in realistic effort required to deal with those issues. It’s a way of contingency planning.

Think of it like yield modeling. You know that on each wafer a certain number of dice will fall out. Yield modeling doesn’t tell you which particle is going to hit which die and where. But they give you an accurate assessment of how your design will yield. Numetrics is like a yield model for project plans. It’s saying there’s a certain probability that if you’re going to try to achieve these targets, given what you’ve input you’re going to fail.

It allows you to make a quantitative assessments. It’s a probability model. It’s not a crystal ball.

Q: How does the complexity calculation model handle predictions for newer nodes, such as 45 and 32nm?

A: Numetrics’ IC Industry Database has collected information for eight technology generations. The technology shifts from one generation to another have been observed before. And what we’ve observed is that early users of technology nodes face considerably more complexity than later users of the same node, once the models and such are more stable. The equation has calibrated this effect which repeats from generation to generation. We’ve been able to model what the effect of the extra technology of a new node will be on a new design.

Q: Can your tools get data from existing sources or do I have to input it manually?

A: We’re dealing with milestones, staffing information and complexity information. Typically this information is copy-pasted from existing sources or customers are using XML import to get data into our tools.

(Alex is Numetrics’ director of professional services).