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    Posts Tagged ‘ Planning ’

    Re-Planning semiconductor design projects effectively

    by Numetrics | August 3, 2009 | In Best Practices, Products, Project Planning, Risk Analysis | No Comments

    Summary: Re-planning a semiconductor design project is often inevitable as the program is underway. The key to effective, productive re-planning lies in understanding complexity, schedule and resources.

    Change is inevitable. Economic factors, mergers and acquisitions, customer specification changes, management and strategy changes all affect project planning and execution. These factors create a need for re-planning IC projects while they are ongoing.

    The key to re-planning is the same as for the original planning process: an understanding of complexity, schedule and resources. Numetrics’ NMX-ERP can capture not only the starting characteristics of your design, but also updates as work is completed. This means that at any point during the design, you can calculate the work remaining and the resource and/or schedule implications of that.

    Re-planning is simply a process of updating the assumptions based on new information. From there it is a simple process to re-run the analysis, and to generate a new plan. This is easy not only because there is explicit support in the tools for re-planning and the management of multiple scenarios for a single design, but also because there is no need for data re-entry. Everything is built from the original plan, saving a great deal of time for your planners.

    Schedule Risk Analyzer generates a comprehensive set of reports that quantitatively assess the underlying schedule risk, given the design’s complexity, staffing assigned to the project and target cycle-time.

    Schedule Risk Analyzer generates a comprehensive set of reports that quantitatively assess the underlying schedule risk, given the design’s complexity, staffing assigned to the project and target cycle-time.

    The real implication of the re-planning capability is that when a change is proposed, you can quickly determine feasibility. For example, if marketing comes to you and says, “We need samples six weeks early for a key customer,” you can rapidly tell them what that means for resources. If additional resources are not available, you might consider scaling back product features to meet the new schedule. Alternatively, you may be forced to complete the design with fewer engineers than you had originally planned for. In such a case, you can quickly determine the best way to meet your business objectives with the new constraint—either reducing the feature set, or planning for a managed schedule slip.

    The net benefit of Numetrics’ re-planning tools is fact-based decision-making in a time of stress. Fact-based planning improves the quality of internal decisions, leading to a healthier business and happier employees. And that can’t be bad.

    How to minimize IC development schedule risk

    by Numetrics | May 5, 2009 | In Best Practices, Project Planning, Risk Analysis, Schedule Predictability | No Comments

    Summary: Risk to IC development schedules can be minimized by comparing design plan assumptions with a database of historical industry designs and your company’s own history of completed projects to help you determine tradeoffs.

    Simply put, schedule risk is the difference between the planned schedule, and the lessons of history. If you plan to finish a design with 20 engineers in 25 weeks, yet industry and corporate comparisons indicate that you need either 27 engineers or to lengthen the schedule to 34 weeks, you have identified schedule risk.

    The Numetrics tools can compare your design plan assumptions with all designs in the industry database, or with a subset based on powerful filters, or most powerfully with your own company’s history of completed design projects. If your plan is more aggressive than the results achieved historically, then you risk missing your schedule. High levels of schedule risk disempower your engineers, because the plan feels unrealistic to them. It also creates business risk, especially if schedule is critical. It doesn’t make sense to agree to a plan that requires productivity much greater than you have historically been able to deliver.

    On the other hand, it is reasonable to set a stretch goal that is a little better than your historical performance or the industry averages. That’s a stretch goal, and if the team believes it’s feasible, they will work hard to achieve it. This is a point where risk is managed, and the goals are achievable. Everyone likes to outperform their peers, but no one wants to be set up for failure.

    By using Numetrics’ tools to analyze schedule risk, you can create a plan that is aggressive, but not so aggressive that it is doomed to fail. Such a plan is good for your team, and good for your business.

    Ensuring schedule predictability for IC designs

    by Numetrics | April 3, 2009 | In Best Practices, Project Planning, Risk Analysis, Schedule Predictability | No Comments


    Summary: Schedule predictability is the art and science of determining the completion date for your semiconductor IC project, based on a statistical model, validated across multiple designs.

    When you plan a project, you are working with incomplete information. Organizational changes, specification changes, technical challenges and more conspire to make it difficult to accurately predict when your new product will be ready.

    Schedule predictability is the art and science of determining the completion date for your project, based on a statistical model, validated across multiple designs. The key ingredients are your design’s complexity, coupled with your resource plan. With these two inputs, Numetrics can significantly improve the accuracy of your schedule predictions. One customer went from consistent overruns to accuracy within a few percent on the first designs they modeled in the Numetrics toolset.

    How is this possible? The core is the Numetrics ability:

    • To understand which factors drive complexity
    • To create a normalized characterization of your design that allows comparison with others.

    When we compare your proposed design with historical productivity and schedule information, we can statistically determine the expected schedule for your new project. The accuracy of the model is enhanced by our industry database of over 1200 designs, coupled with specific information from your company’s historical project record.

    The result is a robust, realistic prediction of the schedule, based on

    • Complexity
    • Resource availability and
    • Historical data.

    The value is a greatly enhanced ability to meet your market windows, time and time again.

    Effective what-if scenario analysis for IC development projects

    by Numetrics | March 17, 2009 | In Best Practices, Industry Database, Products, Project Planning, Risk Analysis, Schedule Predictability | No Comments

    Summary: Comparing the specifics of your semiconductor design with industry and company history enables insightful what-if scenario analysis to help manage development programs effectively .

    During the planning stages for a chip design, there are a number of variables that can be tweaked in the creation of the final product plan. We can reduce or expand the feature set for a new device. We can reduce or extend the schedule. And we can reduce or increase the number of full-time-equivalent (FTE) staff allocated to the project. By manipulating these variables, we can negotiate a plan between the different stakeholders. In some cases, resources are the limiting factor. In others, the schedule is non-negotiable (for example a lot of consumer products must be ready for CES).

    Running a lot of plans against all these variables has historically been difficult and time-consuming. In addition, the results have always been subject to arguments because there has been no trusted model to relate complexity, resources and schedule. Numetrics changes all that. By tweaking resource, schedule or feature set (complexity) assumptions, NMX-ERP can rapidly generate graphs that show the feasibility of each plan, and compare it with company and industry norms using their proprietary complexity engine and plan synthesizer.

    The speed and defensibility of these analyses lends them great power. It is not rational to assume productivity or schedules that are significantly different from past performance, so any feasible plan must lie close to the lessons of history. There is a cost to adding features, or to shrinking the schedule, or to reducing headcount. The most effective way to negotiate these choices is with the aid of an objective toolset that combines the specifics of your design and plan with industry and company history. The tool is fast enough that you can run tens or even hundreds of plans in minutes or hours. From these scenarios you can then pick the plan that best meets your business goals.

    Excellence in Semiconductor Design Productivity

    by Numetrics | February 23, 2009 | In Best Practices, Case Studies | No Comments

    Summary: Everybody wants to increase productivity. But there’s no free lunch: assigning too few resources to a project increases stress and creates schedule risk.

    Productivity excellence is the process of maximizing productivity by setting the most aggressive targets that are still achievable. Achievable targets mean that you will meet your schedule goals. Aggressive means that everyone will be working really hard to get there. The combination ensures that your products will come to market at the earliest possible time, given hard, focused work from a team no larger than you need.

    The value of productivity excellence is felt in three main areas.

    • First, in these tough economic times, you can be sure you haven’t spent money on resources that are not essential to your project.
    • Second, you have set the bar appropriately for an ambitious, capable engineering team.
    • Third, you have controlled schedule risk, and minimized the likelihood of a schedule slip, with potentially disastrous implications for revenues and market share.

    At the end of the day, productivity excellence means meeting your business goals efficiently, with a motivated workforce doing their best to meet an aggressive, but still feasible plan. Take a look at our customer case study involving Innovasic, which maximized its design throughput by benchmarking
    microcontroller development team productivity.

    What is industry-norm effort for semiconductor designs?

    by Numetrics | February 14, 2009 | In Products, Project Planning, Risk Analysis, Schedule Predictability | No Comments

    Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

    Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

    From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

    We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

    But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

    • We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

    This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.

    How do you quantify design complexity?

    by Numetrics | January 23, 2009 | In Products, Project Planning, Risk Analysis, Schedule Predictability | No Comments


    Summary: Design complexity can be quantified and communicated in a way that makes IC projects predictable and more productive.

    It doesn’t take a rocket scientist to know that the resources and time required to build a chip vary from one design to another. The variation is a function of how difficult the chip will be to build. We measure that and call it complexity.

    The hard part, however, is to know which attributes of the design correlate to the effort required to build the chip.

    • Is clock speed important?
    • What about the number of transistors?
    • Re-use?
    • Analog and mixed signal?
    • Voltage islands?
    • Modes?

    The list goes on and on. One of the reasons why the NMX-ERP™ software suite accurately forecasts the time and resource requirements for a design is that our engineers, using more than a thousand design projects, have developed a deep understanding of just how hard a given project may be so your engineers can be more productive.

    Knowing how to translate chip-design attributes into complexity is the foundation of apples-to-apples comparisons between designs. That’s critical to making sure your latest design can be compared with other industry designs, as well as designs your company has done in the past. After taking in all the complexity factors as chip specifications, Numetrics’ engines can reliably and rapidly calculate the relative complexity of your design, as compared with every other design in our industry database. That’s the foundation upon which all the plan synthesis, what-if scenario analysis, re-planning and root-cause analysis capabilities of NMX-ERP are built.

     
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