By Jeffrey Eversmann
After two years of doom and gloom, it’s refreshing to attend an industry event and hear talk of innovation—at all levels. That was the atmosphere at a recent GSA Silicon Series luncheon I attended in Austin, Texas, that featured a panel discussion on blurring technology lines.

At the application-segment level, Patrick Moorhead, marketing vice president with AMD, joked:

“I’ve been hearing that the desktop market is dying for the past 15 years.”

He made that quip after holding up the “4th screen” examples he had brought with him: an iPad and a Sony eBook reader. “Only 5-10% of consumers back up their data, so a fixed device will always be in the home,” Moorhead said.

I agree. While I like the professional security that a proliferation of leading-edge microprocessors brings, I am burdened by the yearly upgrade rotation I am now on to keep current the six-plus PCs in my home. All of us in the semiconductor industry have been through multiple iterations of the tablet device, some of them from Apple. As was often said by the panel, “it’s not an either-or these days.”

Fellow panelist Naveed Sherwani, CEO of Open-Silicon, Inc., added “the new form factor will succeed if it is useful.” So, panelists agreed that the iPad is not a desktop (or even laptop) killer. The question is: Will the average consumer add yet another device to the list of electronic gadgets we carry around each day?

The panel shifted to the technology level and wrestled with an intriguing question: Will ARM replace x86 in the desktop or will x86 replace ARM in the SoC market? While some in the audience checked email on their smartphones, Sandeep Shah, director of marketing and applications at Marvell Semiconductor, Inc., and Sherwani tackled the question.

Shah argued that an “ARM architecture licensee can bring together the best of both worlds.” (This is a very interesting perspective in light of Apple’s recent purchase of Intrinsity, which worked with Samsung to develop the ARM Cortex-based A4 processor.)

Shifting processor sands

Sherwani was quick to add that while there really hasn’t been an attempt by x86 to take over SoC design, that doesn’t mean an attempt isn’t brewing:

“In the next three years or so, things will get more competitive and more intense, when x86 is available for SoC development.”

Then it was time to move on to another much-discussed technology challenge, low power design. The panel members pulled out their different battery-powered devices and rattled off the actual vs. published battery life. “What we really need is more disclosure, a ‘truth-in-battery-life’ from silicon providers,” Moorhead said.

Shah, who probably lives power issues on a daily basis, talked about how the different Blackberry models used different chips from Marvell to get different power performance in the system. Marvell focuses on both system-level and gate-level approaches to power management. Sherwani wrapped things up from a design perspective saying “we have just scratched the surface on lower power design.” Maybe what we need is a Moore’s Law for low power design – something that will challenge engineers to do things that today are viewed as impossible.

All in all, the GSA luncheon was a great opportunity to re-connect with fellow semiconductor engineers. We exchanged cards with the same cell phone numbers, but with new company names, new titles, and new addresses. We talked about how tough things have been but how happy we are to be traveling less and spending more time with our families.

It felt like the calm before the innovation storm. I don’t know about you, but I’m here and getting ready for it.

By Ron Collett

The latest venture capital investment figures are out from PricewaterhouseCoopers’ MoneyTree and the National Venture Capital Association (NVCA). They’re not pretty.

VCs spent just $17.7 billion on 2,795 deals last year. That’s down 36 percent from $27.9 billion in 2008, and it represents the lowest dollar amount and number of investments since 1997.

The chart I pulled together above, based on that data, shows the quarterly VC investment trends for semiconductor companies in just the past three years. Not an encouraging trend line. Total VC investment last year in our industry was $771 million, compared with a peak of $3.4 billion in 2000. What a difference a decade makes.

This realignment of dollars has brought about new expectations from investors and from semiconductor vendors.

Speaking to The Wall Street Journal last week, Bob Ackerman, a venture capitalist at Allegis Capital in Palo Alto, said:

We’re preoccupied by capital efficiency.

Those two words, “capital efficiency,” speak directly to the semiconductor industry’s challenge. This focus on capital efficiency is why semiconductor vendors should be increasingly preoccupied with boosting engineering productivity to get the most from their R&D budget. Lacking an internal fab for differentiation in the fabless era, companies are looking for new ways to gain competitive advantage, and they’re training their sights on their R&D organizations.

The industry’s best-in-class semiconductor IDMs in fact have jumped on this imperative, especially as many of them have shed the last of their owned fabs and now need to compete with fabless companies.

But it works the other way too: Long-time fabless players suddenly find big new competitors that have shed their fabs. They too are looking to boost product-development productivity to stay one step ahead of their new competition.

It’s clear the days of big-time investment are a thing of the past. Today, good companies are those with innovative product ideas; great companies are those that also drive highly productive R&D organizations to get those products completed on predictable schedules and to market ahead of the competition to realize higher returns.

By Alex Silbey

(Summary: We inevitably get questions about Numetrics’ technology after webinars or live event presentations, and we’d like to share some of them in the spirit of helping you understand more about our products and solutions. Here are answers to several recent questions in the virtual mail bag).

Q: How do you define productivity?

A: We calculate complexity of the project and we divide the complexity units by total number of person weeks required to get that product out to volume production. That quotient gives you the productivity number. The typical range is 500 on the low end for a large team to 3000 for a small team.

There’s another measure, which is throughput, and throughput is complexity units per week. That’s a measure of normalized cycle team. Productivity is efficiency of the team and higher number is better.

Q: I’ve heard that in some sectors productivity decreases as team size increases. Is this true in semiconductor product development?

A: It’s a universal effect across pretty much any activity that has to do with building things. When you build larger teams, each person is doing a smaller and smaller slice of the overall work. More work has to be split apart and then put back together. Bigger teams equal more meetings and more management required. It’s universal and it’s inevitable. With the Numetrics approach, you can minimize this effect—decreasing productivity curve is flatter than it would otherwise be.

Q: It’s impossible to predict in a design project how many times customer requirements will change, when your EDA tools go buggy or if a key contributor leaves the team. So how do you quantify schedule risk with so many unpredictable variables?

A: The simple answer is our tools don’t predict things. You have a draw a line between statistical analysis and a crystal ball.

What Numetrics’ tools do is take your inputs of design parameters and measure them against the history of more than 1,500 design projects over eight generations of technology evolution (here’s a link to a demo of our tools). Using the data from those hundreds and hundreds of designs, this builds in realistic effort required to deal with those issues. It’s a way of contingency planning.

Think of it like yield modeling. You know that on each wafer a certain number of dice will fall out. Yield modeling doesn’t tell you which particle is going to hit which die and where. But they give you an accurate assessment of how your design will yield. Numetrics is like a yield model for project plans. It’s saying there’s a certain probability that if you’re going to try to achieve these targets, given what you’ve input you’re going to fail.

It allows you to make a quantitative assessments. It’s a probability model. It’s not a crystal ball.

Q: How does the complexity calculation model handle predictions for newer nodes, such as 45 and 32nm?

A: Numetrics’ IC Industry Database has collected information for eight technology generations. The technology shifts from one generation to another have been observed before. And what we’ve observed is that early users of technology nodes face considerably more complexity than later users of the same node, once the models and such are more stable. The equation has calibrated this effect which repeats from generation to generation. We’ve been able to model what the effect of the extra technology of a new node will be on a new design.

Q: Can your tools get data from existing sources or do I have to input it manually?

A: We’re dealing with milestones, staffing information and complexity information. Typically this information is copy-pasted from existing sources or customers are using XML import to get data into our tools.

(Alex is Numetrics’ director of professional services).

(Summary: A clever YouTube video highlights how communications disconnects can prompt IC product-development projects to slip schedule).

By Ron Collett

We talk a lot about schedule predictability and maximizing IC design throughput. That’s what we do as part of our goal to help product-development teams improve productivity and ROI. But there’s another, more subtle goal, and that’s improving engineering communications and expectations.

Engineers will work most productively when given an aggressive schedule if they know it to be realistic because it’s rooted in fact-based planning. With unrealistic schedule assumptions, the reaction is “been there, done that,” and productivity—and ultimately morale—suffers.

This dynamic is vibrantly illustrated in a YouTube video inspired and narrated by Jasper Design Automation CEO Kathryn Kranen, called How Engineers Communicate: A Video Parody.

In it, the mythical company WonderChips is planning its T-1000 communications device. The video takes us through the planning process, the assumptions and most importantly the communications disconnects engineers and executives encounter along the way.

To summarize the story line:

• In the beginning, Rakesh determines that the T-1000 device is four times more complex than its predecessor and therefore a new EDA tool is needed to speed this project to completion on schedule. His boss, however, rejects the investment.

• Next, the T-1000 team grabs a conference room to begin its bottom-up planning approach, fueled by chips and soda and catered food. Hours go by, punctuated by arguments over how long certain blocks will take to design.

• Eventually, the team leader seems satisfied. She tells the group, “Assuming all these assumptions hold, I think the schedule looks really good.” The team agrees, and the leader goes off to present the schedule to executive management.

• Later, she returns to the team with good news and bad news: The good news is the executive staff loves the feature set. Bad news is the T-800, another project, is slipping schedule, and there’s competitive pressure in the market. So the executives want the T-1000 to sample months sooner than the team’s bottom-up plan called for. Oh, and they need to beef up the memory subsystem while they’re at it.

Says the team leader: “I know as a team we can do this. You guys with me?”

The team groans. As the engineers exit the conference room, shaking their heads in disbelief, one engineer murmurs: “It will be done when it is done.”

The T-1000 ends up slipping by at more than six months, and the executive who turned down the tool investment demands tape out at any cost.

From my perspective, WonderChips would have benefited by complementing its bottom-up scheduling approach with a top-down methodology—using quantified estimates of the chip’s complexity, the team’s productivity and a model of the rate at which effort will be expended on the project.

It would have helped engineers and management communicate in a common language and build an aggressive yet achievable schedule. And it would saved WonderChips’ management from having to extend the on-site day care closing time to midnight to get the chip done.

(Summary: More than 80 percent of semiconductor projects slip schedule, but we can change this costly reality by introducing a fact-based planning methodology into semiconductor product-development organizations).

By Ron Collett

The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

Here’s a sampling of the presentations:

• “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
• “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
• “Energy Efficient Design at 65nm – What Really Works!”

And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

Wrong.

Projects slip for a number of reasons:

• We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
• We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
• Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

Typical bottom-up reactions to managing such complexity tend to fall into two categories:

• Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
• Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

• Quantified estimates of the chip’s complexity
• The team’s productivity
• A model of the rate at which effort will be expended on the project.

With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

(Summary: For semiconductor companies, differentiation has shifted from manufacturing to improving productivity in new-product development. That realization is the easy part; getting there requires help.)

By Ron Collett

I’m always impressed with the level of optimism I find at semiconductor industry events around the world. There may be pockets of gloom about the state of the semiconductor industry, but executives certainly don’t share it. Yes, it’s not the same industry it was 10 years ago, but, no, it’s not doomed. Far from it: The dynamics are just different.

That was my message when I presented last week at Malcolm Penn’s International Electronics Forum in Geneva. Here’s why the dynamics are different:

• The industry head count has shrunk 30 percent this decade
• Industry consolidation has picked up pace
• Cost-cutting is rampant
• There’s more pressure than ever on design teams to get great products out the door on time and on budget

Here’s how the dynamics are different: Differentiation has shifted as industry disaggregation has reached an end state. There was a time when a semiconductor company differentiated itself through manufacturing and process technology (or way back when, through making its own steppers!) No longer.

So where’s the differentiation? It’s not in cost-cutting. Everyone’s doing that.

Differentiation has shifted to the heart of the semiconductor company’s value proposition: its new-product development.

Electronics Weekly’s David Manners, in his coverage of IEF last week (“What’s the Answers to the Chip Industry’s Problems? Ask IEF”), touched on how profound this can be. He quoted Alain Dutheil, CEO of ST-Ericsson, as saying 85 percent of his 8,000 employees are in R&D.

The other part of the story, which we’ve blogged about, is that most SOC projects slip schedule and most IC teams tend to underestimate their product R&D costs.

That brings me back to our IEF presentation (“Raising the Bar on Semiconductor R&D Management, Execution, and ROI”), which we created in partnership with PRTM, one of the world’s premier operational strategy consulting firms (with deep ties to the IC industry).

Our three take-aways were:

• The bar is being significantly raised on semiconductor R&D management, execution, and achieving ROI
• Companies must continuously progress through the stages of maturity to thrive (functional, project, portfolio, and cross-enterprise excellence)
• Fact-based planning is a critical foundation for ongoing NPD success

Anyone can cut costs in challenging times but winning companies find news ways to differentiate themselves, and they are the companies that come out of recessions stronger than their competition.