By Ron Collett

In December, we were honored to participate in a Design & Reuse panel in Grenoble, France, titled “IP Reuse vs. IP Leverage: What’s the difference and what are the issues?”

Andrea Fortunato, our European director of professional services, represented us and gave an overview of the particular challenges that design reuse brings. He blogged about it right after the panel (Design Reuse: It’s Harder Than it Looks).

Our friends at D&R have just posted an audio Webinar of that panel. It’s definitely worth a listen if you’re designing with cores and trying to take advantage of reusability.

Have you had design reuse challenges recently? If so, feel free to comment on this post to let us know what they were and how you overcame them. Improving productivity in the semiconductor industry is a communal effort!

(Summary: A clever YouTube video highlights how communications disconnects can prompt IC product-development projects to slip schedule).

By Ron Collett

We talk a lot about schedule predictability and maximizing IC design throughput. That’s what we do as part of our goal to help product-development teams improve productivity and ROI. But there’s another, more subtle goal, and that’s improving engineering communications and expectations.

Engineers will work most productively when given an aggressive schedule if they know it to be realistic because it’s rooted in fact-based planning. With unrealistic schedule assumptions, the reaction is “been there, done that,” and productivity—and ultimately morale—suffers.

This dynamic is vibrantly illustrated in a YouTube video inspired and narrated by Jasper Design Automation CEO Kathryn Kranen, called How Engineers Communicate: A Video Parody.

In it, the mythical company WonderChips is planning its T-1000 communications device. The video takes us through the planning process, the assumptions and most importantly the communications disconnects engineers and executives encounter along the way.

To summarize the story line:

• In the beginning, Rakesh determines that the T-1000 device is four times more complex than its predecessor and therefore a new EDA tool is needed to speed this project to completion on schedule. His boss, however, rejects the investment.

• Next, the T-1000 team grabs a conference room to begin its bottom-up planning approach, fueled by chips and soda and catered food. Hours go by, punctuated by arguments over how long certain blocks will take to design.

• Eventually, the team leader seems satisfied. She tells the group, “Assuming all these assumptions hold, I think the schedule looks really good.” The team agrees, and the leader goes off to present the schedule to executive management.

• Later, she returns to the team with good news and bad news: The good news is the executive staff loves the feature set. Bad news is the T-800, another project, is slipping schedule, and there’s competitive pressure in the market. So the executives want the T-1000 to sample months sooner than the team’s bottom-up plan called for. Oh, and they need to beef up the memory subsystem while they’re at it.

Says the team leader: “I know as a team we can do this. You guys with me?”

The team groans. As the engineers exit the conference room, shaking their heads in disbelief, one engineer murmurs: “It will be done when it is done.”

The T-1000 ends up slipping by at more than six months, and the executive who turned down the tool investment demands tape out at any cost.

From my perspective, WonderChips would have benefited by complementing its bottom-up scheduling approach with a top-down methodology—using quantified estimates of the chip’s complexity, the team’s productivity and a model of the rate at which effort will be expended on the project.

It would have helped engineers and management communicate in a common language and build an aggressive yet achievable schedule. And it would saved WonderChips’ management from having to extend the on-site day care closing time to midnight to get the chip done.