By Ron Collett

The concept seems simple: The more ip blocks you re-use in an IC or system design, the faster and more productively you’ll get your design done. The ITRS roadmap began identifying the benefits as long ago as 1997, showing the industry could reasonably expect 56,000 gates per designer per year when using large ip blocks (75,000-1 million gates). By 2007 that figure was up to 600,000 gates per designer per year, a tenfold increase.

There’s no doubt design reuse is here to stay. In 2007, a third of all logic was reused design blocks. That’s expected to rise to nearly 50 percent by 2015, according to the ITRS.

The numbers and the theory behind it are encouraging, but reality is much different. Making 30 percent of your design from reused IP blocks doesn’t mean you’re going to be 30 percent more productive at the end of the project. That’s because IC design teams tend to underestimate the work needed to implement the reused IP. This can cause project delays and missed market opportunities.

The challenge is that it’s very difficult to estimate design complexity, especially the impact of reuse. IC design schedules can falter because of the inability to estimate the impact of IP modifications on project effort.

Even a small percentage of reuse can add outsized effort to a development project. For example, if you add one new block of 600,000 gates to a 6 million-gate design, you’re adding 10 percent to the IC but increasing the effort required on the project by 24 percent. Adding 10 percent new circuitry to all blocks in that 6 million-gate design—with 90 percent of each block being re-used—doubles the effort required on the project, even though it increases the IC size by just 10 percent to 6.6 million gates.

This issue will be part of a larger discussion Dec. 1 at IP-ESC 2009 in Grenoble. We were invited to sit on a panel—“IP Reuse vs. IP Leverage: What’s the difference, and what are the issues?”—with Kathryn Kranen, CEO of Jasper Design Automation, and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics. Our director of professional services, Andrea Fortunato, will represent Numetrics.

This is a well-timed panel in my opinion because re-use is an issue that transcends the industry and is crucial for its future. And how we go about optimizing design re-use is crucial to manage today.

By Alex Silbey

(Summary: We inevitably get questions about Numetrics’ technology after webinars or live event presentations, and we’d like to share some of them in the spirit of helping you understand more about our products and solutions. Here are answers to several recent questions in the virtual mail bag).

Q: How do you define productivity?

A: We calculate complexity of the project and we divide the complexity units by total number of person weeks required to get that product out to volume production. That quotient gives you the productivity number. The typical range is 500 on the low end for a large team to 3000 for a small team.

There’s another measure, which is throughput, and throughput is complexity units per week. That’s a measure of normalized cycle team. Productivity is efficiency of the team and higher number is better.

Q: I’ve heard that in some sectors productivity decreases as team size increases. Is this true in semiconductor product development?

A: It’s a universal effect across pretty much any activity that has to do with building things. When you build larger teams, each person is doing a smaller and smaller slice of the overall work. More work has to be split apart and then put back together. Bigger teams equal more meetings and more management required. It’s universal and it’s inevitable. With the Numetrics approach, you can minimize this effect—decreasing productivity curve is flatter than it would otherwise be.

Q: It’s impossible to predict in a design project how many times customer requirements will change, when your EDA tools go buggy or if a key contributor leaves the team. So how do you quantify schedule risk with so many unpredictable variables?

A: The simple answer is our tools don’t predict things. You have a draw a line between statistical analysis and a crystal ball.

What Numetrics’ tools do is take your inputs of design parameters and measure them against the history of more than 1,500 design projects over eight generations of technology evolution (here’s a link to a demo of our tools). Using the data from those hundreds and hundreds of designs, this builds in realistic effort required to deal with those issues. It’s a way of contingency planning.

Think of it like yield modeling. You know that on each wafer a certain number of dice will fall out. Yield modeling doesn’t tell you which particle is going to hit which die and where. But they give you an accurate assessment of how your design will yield. Numetrics is like a yield model for project plans. It’s saying there’s a certain probability that if you’re going to try to achieve these targets, given what you’ve input you’re going to fail.

It allows you to make a quantitative assessments. It’s a probability model. It’s not a crystal ball.

Q: How does the complexity calculation model handle predictions for newer nodes, such as 45 and 32nm?

A: Numetrics’ IC Industry Database has collected information for eight technology generations. The technology shifts from one generation to another have been observed before. And what we’ve observed is that early users of technology nodes face considerably more complexity than later users of the same node, once the models and such are more stable. The equation has calibrated this effect which repeats from generation to generation. We’ve been able to model what the effect of the extra technology of a new node will be on a new design.

Q: Can your tools get data from existing sources or do I have to input it manually?

A: We’re dealing with milestones, staffing information and complexity information. Typically this information is copy-pasted from existing sources or customers are using XML import to get data into our tools.

(Alex is Numetrics’ director of professional services).

(Summary: A clever YouTube video highlights how communications disconnects can prompt IC product-development projects to slip schedule).

By Ron Collett

We talk a lot about schedule predictability and maximizing IC design throughput. That’s what we do as part of our goal to help product-development teams improve productivity and ROI. But there’s another, more subtle goal, and that’s improving engineering communications and expectations.

Engineers will work most productively when given an aggressive schedule if they know it to be realistic because it’s rooted in fact-based planning. With unrealistic schedule assumptions, the reaction is “been there, done that,” and productivity—and ultimately morale—suffers.

This dynamic is vibrantly illustrated in a YouTube video inspired and narrated by Jasper Design Automation CEO Kathryn Kranen, called How Engineers Communicate: A Video Parody.

In it, the mythical company WonderChips is planning its T-1000 communications device. The video takes us through the planning process, the assumptions and most importantly the communications disconnects engineers and executives encounter along the way.

To summarize the story line:

• In the beginning, Rakesh determines that the T-1000 device is four times more complex than its predecessor and therefore a new EDA tool is needed to speed this project to completion on schedule. His boss, however, rejects the investment.

• Next, the T-1000 team grabs a conference room to begin its bottom-up planning approach, fueled by chips and soda and catered food. Hours go by, punctuated by arguments over how long certain blocks will take to design.

• Eventually, the team leader seems satisfied. She tells the group, “Assuming all these assumptions hold, I think the schedule looks really good.” The team agrees, and the leader goes off to present the schedule to executive management.

• Later, she returns to the team with good news and bad news: The good news is the executive staff loves the feature set. Bad news is the T-800, another project, is slipping schedule, and there’s competitive pressure in the market. So the executives want the T-1000 to sample months sooner than the team’s bottom-up plan called for. Oh, and they need to beef up the memory subsystem while they’re at it.

Says the team leader: “I know as a team we can do this. You guys with me?”

The team groans. As the engineers exit the conference room, shaking their heads in disbelief, one engineer murmurs: “It will be done when it is done.”

The T-1000 ends up slipping by at more than six months, and the executive who turned down the tool investment demands tape out at any cost.

From my perspective, WonderChips would have benefited by complementing its bottom-up scheduling approach with a top-down methodology—using quantified estimates of the chip’s complexity, the team’s productivity and a model of the rate at which effort will be expended on the project.

It would have helped engineers and management communicate in a common language and build an aggressive yet achievable schedule. And it would saved WonderChips’ management from having to extend the on-site day care closing time to midnight to get the chip done.

(Summary: More than 80 percent of semiconductor projects slip schedule, but we can change this costly reality by introducing a fact-based planning methodology into semiconductor product-development organizations).

By Ron Collett

The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

Here’s a sampling of the presentations:

• “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
• “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
• “Energy Efficient Design at 65nm – What Really Works!”

And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

Wrong.

Projects slip for a number of reasons:

• We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
• We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
• Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

Typical bottom-up reactions to managing such complexity tend to fall into two categories:

• Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
• Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

• Quantified estimates of the chip’s complexity
• The team’s productivity
• A model of the rate at which effort will be expended on the project.

With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

The phrase “top gun” generally refers to hot-shot fighter pilots performing amazing feats high in the sky, but increasingly it’s being used to describe great engineering managers doing amazing things on land. Numetrics has put together an online seminar covering the best practices of leading IC project planners.

The webinar describes eight techniques used by top-gun engineering managers, followed by a demonstration of Numetrics’ NMX-ERP™ solution and IC Industry Database containing more than 1400 completed IC designs from multiple industry segments.

The webinar presented the following best practices:

1. Computing IC complexity statistically
2. Estimation of resource requirements based on models
3. Rigorous “what-if” analysis for schedule / resource optimization
4. Benchmarking project execution assumptions
5. Determining the most aggressive, yet achievable project plan
6. Quantitatively assessing the schedule / resource implications of each feature request
7. Performing root-cause analysis at the project close milestone
8. Foreseeing resource shortfalls across the project pipeline.

The demonstration showed a live application of the Numetrics toolset, through a realistic scenario involving balancing IC specification and resource availability in the context of a fixed schedule.

You may view the webinar at http://techonline.stream57.com/numetrics/.

For more information, please e-mail info@numetrics.com

Summary: Schedule predictability is the art and science of determining the completion date for your semiconductor IC project, based on a statistical model, validated across multiple designs.

When you plan a project, you are working with incomplete information. Organizational changes, specification changes, technical challenges and more conspire to make it difficult to accurately predict when your new product will be ready.

Schedule predictability is the art and science of determining the completion date for your project, based on a statistical model, validated across multiple designs. The key ingredients are your design’s complexity, coupled with your resource plan. With these two inputs, Numetrics can significantly improve the accuracy of your schedule predictions. One customer went from consistent overruns to accuracy within a few percent on the first designs they modeled in the Numetrics toolset.

How is this possible? The core is the Numetrics ability:

• To understand which factors drive complexity
• To create a normalized characterization of your design that allows comparison with others.

When we compare your proposed design with historical productivity and schedule information, we can statistically determine the expected schedule for your new project. The accuracy of the model is enhanced by our industry database of over 1200 designs, coupled with specific information from your company’s historical project record.

The result is a robust, realistic prediction of the schedule, based on

• Complexity
• Resource availability and
• Historical data.

The value is a greatly enhanced ability to meet your market windows, time and time again.

Summary: Comparing the specifics of your semiconductor design with industry and company history enables insightful what-if scenario analysis to help manage development programs effectively .

During the planning stages for a chip design, there are a number of variables that can be tweaked in the creation of the final product plan. We can reduce or expand the feature set for a new device. We can reduce or extend the schedule. And we can reduce or increase the number of full-time-equivalent (FTE) staff allocated to the project. By manipulating these variables, we can negotiate a plan between the different stakeholders. In some cases, resources are the limiting factor. In others, the schedule is non-negotiable (for example a lot of consumer products must be ready for CES).

Running a lot of plans against all these variables has historically been difficult and time-consuming. In addition, the results have always been subject to arguments because there has been no trusted model to relate complexity, resources and schedule. Numetrics changes all that. By tweaking resource, schedule or feature set (complexity) assumptions, NMX-ERP can rapidly generate graphs that show the feasibility of each plan, and compare it with company and industry norms using their proprietary complexity engine and plan synthesizer.

The speed and defensibility of these analyses lends them great power. It is not rational to assume productivity or schedules that are significantly different from past performance, so any feasible plan must lie close to the lessons of history. There is a cost to adding features, or to shrinking the schedule, or to reducing headcount. The most effective way to negotiate these choices is with the aid of an objective toolset that combines the specifics of your design and plan with industry and company history. The tool is fast enough that you can run tens or even hundreds of plans in minutes or hours. From these scenarios you can then pick the plan that best meets your business goals.

Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

• We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.

Summary: Design complexity can be quantified and communicated in a way that makes IC projects predictable and more productive.

It doesn’t take a rocket scientist to know that the resources and time required to build a chip vary from one design to another. The variation is a function of how difficult the chip will be to build. We measure that and call it complexity.

The hard part, however, is to know which attributes of the design correlate to the effort required to build the chip.

• Is clock speed important?
• What about the number of transistors?
• Re-use?
• Analog and mixed signal?
• Voltage islands?
• Modes?

The list goes on and on. One of the reasons why the NMX-ERP™ software suite accurately forecasts the time and resource requirements for a design is that our engineers, using more than a thousand design projects, have developed a deep understanding of just how hard a given project may be so your engineers can be more productive.

Knowing how to translate chip-design attributes into complexity is the foundation of apples-to-apples comparisons between designs. That’s critical to making sure your latest design can be compared with other industry designs, as well as designs your company has done in the past. After taking in all the complexity factors as chip specifications, Numetrics’ engines can reliably and rapidly calculate the relative complexity of your design, as compared with every other design in our industry database. That’s the foundation upon which all the plan synthesis, what-if scenario analysis, re-planning and root-cause analysis capabilities of NMX-ERP are built.