Semiconductor organizations are accustomed to doing “bottom-up” project planning. Bottom-up project planning itemizes tasks and orders them in time, either in parallel or sequentially. This inherently poses two challenges:
- Trying to catalog every task and
- Estimating the duration of each task.
This may work satisfactorily for well-defined tasks and some phases of the project, but it tends to overlook the unexpected and under-represent the more variable periods of project activity. The consequence is poor schedule predictability.
Numetrics’ approach is inherently different from, but complementary to, bottom-up planning. Like top-down design, which enables IC development teams to design circuits at a high level of abstraction, such as RTL (Register Transfer Level), Numetrics’ Project Plan Synthesis technology uses a fact-based approach from the top down to estimate project staffing requirements and development cycle time. It models the IC development cycle as a stochastic process, in which estimates of resources and schedules are based on the project’s complexity.
Engineering managers provide a high-level description of the project that characterizes the chip’s design complexity. The synthesis engine decomposes this information to generate accurate, statistically-based, estimates of the time and effort the average team in the industry would require, from concept phase to release-to-production, to design that chip.
Modeling IC Development as a Stochastic Process
A good example of IC development’s stochastic nature is the additional time and effort triggered by:
- Unanticipated spec changes
- Library characterization & manufacturing process flaws
- EDA software bugs
- IP quality levels
- Logic design errors and other unpredictable events.
All of this is built into the model, as all projects have unpredictable things happen to them, but treating the development cycle as a stochastic process and therefore modeling its randomness, is the cornerstone for achieving good schedule predictability.
Although it’s impossible to know for sure which random events will occur or their individual impact, it is a foregone conclusion that almost every project will experience a certain number of them that will cause schedule slip. The project modeling challenge is similar to modeling manufacturing yield–process manufacturing specialists compute and plot the probability of a random defect on a die of a certain size, even though neither the particular defect nor its occurrence on a specific wafer or die is known. However, one of the key things specialists know is die size, and from this and other statistical data, process experts can accurately predict the number of good vs. bad die on a wafer.
Numetrics synthesis solution uses similar approach, except instead of using die size to predict yield, the model uses design complexity to predict project effort and duration. The model analyzes the technical characteristics of the design and calculates complexity, which is expressed as industry norm effort. What makes this possible is Numetrics’ Industry Database of more than 1,600 IC projects, which calibrates the complexity calculation algorithms. In the absence of a large database, developing a reliable stochastic model is nearly impossible. The industry database coupled with Numetrics’ modeling expertise is what makes the solution unique.
With Numetrics’ solution, engineering managers quickly determine the industry norm effort for the particular chip design undergoing planning. This provides an excellent starting point for generating a reliable staffing plan and schedule. The industry norm effort is the amount of effort the average development team in the industry would spend on the project, from concept to release-to-production. The manager then adjusts the industry norm estimate to reflect the specifics of his or her particular project and team. The amount of adjustment is based on the manager’s specific knowledge of the development team and a few benchmarks of prior performance. This yields a precise estimate of the effort the particular team will need to expend on the project.
This type of reality-based estimate is defined by the execution performance achieved on prior projects having similar characteristics. Numetrics’ fact-based approach can be reliably applied earlier in the process than bottom-up planning and with little effort, to help guide product direction and make better choices.
The Industry Database calibrates Numetrics’ proprietary IC design complexity normalization engine and estimation models and is the kernel of the NMX-ERP software suite. The patented complexity calculation engine is unique in the industry. Leveraging the Database, the models accurately estimate the amount of effort and time required to develop an IC, from concept to volume production. The models drive Numetrics’ risk analysis and project planning tools, which have been applied to over 500 production IC projects and provide semiconductor development organizations with unprecedented schedule reliability and predictability.