Calculating Design Complexity
The IC Design Complexity Calculation Engine quantifies the complexity of designing a particular chip. The calculation is performed through extensive analysis of the chip’s technical characteristics. The engine supports virtually any kind of semiconductor application, including communications, computing, multimedia, industrial and automotive, regardless of whether the project is a small analog device or complex processor.
The models comprising the engine are regularly recalibrated to reflect changes in:
- IC design
- Engineering skills
- Design methodology
- And more.
Comprehensive, Targeted Inputs
To accurately and reliably quantify design complexity, Numetrics’ calculation engine analyzes the target design’s technical characteristics (see chart below) – those revealed through extensive data mining of its NMX IC Industry DatabaseTM to have a statistically significant impact on engineering effort. The Database comprises more than 1,600 IC projects from more than 75 semiconductor and electronics companies. The engine’s accuracy is the foundation for generating reliable project estimations – resource requirements, development cycle times and key performance indicators such as productivity and throughput.
Underpinning the engine is a model that calculates “industry-standard effort”– the amount of effort the average development team in the industry would spend on that design, from start-of-concept to release-to-volume production. The calculation of industry standard effort is the basis for reliably measuring complexity.
Initial complexity estimates are available with less than an hour of work via the engine’s powerful Quickstart front-end. Typical accuracy is +/-15 percent compared with the more detailed data entry option (which normally takes two to eight hours). With QuickStart, users enter a small but highly select subset of the design’s technical characteristics –those shown statistically to have the greatest impact on project effort.
The engine analyzes each of the blocks comprising the chip. Block-level complexity analysis results are combined with the chip-level complexity model, where they are analyzed together to calculate the final design complexity value.
Contact us: firstname.lastname@example.org