NMX IC Schedule Risk Analyzer™

The NMX Schedule Risk Analyzer™ quantitatively determines the likelihood that an IC project’s development schedule can be achieved.

Built into IC Project Planner, Schedule Risk Analyzer leverages Numetrics’ IC Industry Database, which contains more than 1,700 benchmarked integrated circuit (IC) projects and yields a statistically valid baseline for generating quantitative risk analyses.

Schedule Risk Analyzer uses a unique approach in quantifying risk. Instead of relying on the manager to subjectively quantify schedule risk factors, the tool:

• Calculates the target chip’s design complexity using Numetrics’ patented design complexity calculation technology and simultaneously analyzes both the manpower and time budgeted to the project.
• With that information, it calculates the productivity assumed in the project plan and compares it against both the industry norm and that particular organization’s past performance. The comparison enables managers to quickly assess whether the schedule is realistic, given the complexity of the design and the manpower and time budgeted. (The diagrams below illustrate the inputs and outputs of the tool).

Risk Analyzer operates by calculating not only the development productivity implied in the project plan, but also the implied development throughput. It calculates the development throughput that the project team must achieve to meet its target schedule. Development throughput is the output rate of the development team i.e. how much work product the development team outputs per week. Managers can immediately observe if the implied throughput in the project plan is significantly greater than either the industry norm or that organization’s past performance.

Evaluate Project Assumptions

Risk Analyzer also enables managers to quickly evaluate other important underlying assumptions in the project plan and compare them with historical performance and industry norms for that particular kind of chip. These include:

• Spin count
• Cycle times
• Duration between important project milestones that are standard for that particular kind of chip.

The tool automatically produces Risk Report Sets of all metrics needed to rigorously assess a project plan, enabling managers to run risk analyses based on a full range of project scenarios.

With Risk Analyzer, managers also can record and update the primary risk factors affecting their projects—factors that could lead to schedule slip or the need for more resources—such as unstable specs, new manufacturing processes, untested libraries or unproven third-party IP. This capability provides a simple and powerful way to document and communicate each risk associated with a project, its potential impact, and the action planned to mitigate the risk.

Figure 1. Schedule Risk Analyzer generates a comprehensive set of reports that quantitatively assess the underlying schedule risk, given the design’s complexity, staffing assigned to the project and target cycle-time.

Figure 2. The power curve, fit to the data, shows the IC development productivity that can be expected for IC teams of different sizes. The target project (shown as a triangle) is in its planning phase and is assuming a productivity calculated by Risk Analyzer from the project’s plan that is 4.5 times higher than the norm for teams of that size. It’s a lofty goal that the team is unlikely to achieve, which makes the risk of schedule miss nearly certain.