NMX IC Project Planner™
Used on more than 1000 IC projects in the semiconductor industry, NMX IC Project Planner™ uses Numetrics’ proprietary project plan synthesis technology to automatically generate accurate estimates of development cycle time and staffing requirements, from product concept to release-to-production. Calculations are based on:
- The complexity of the chip
- The calibration of the development team
- The project’s staffing strategy.
In addition to generating estimates of cycle time and staffing, the tool’s “what-if” simulation environment enables users to rapidly perform tradeoffs between the critical constraints on the project–cycle time vs. staffing-level, chip functionality & performance.
At the heart of IC Project Planner is a stochastic model of the IC development process. Based on this model, IC Project Planner calculates the complexity of the chip and expresses it as industry norm project effort. This is the amount of effort the average team in the industry would expend on that particular project.
To calculate how much effort and time the manager’s team will likely expend on the project, IC Project Planner uses the project manager’s calibration of the team’s anticipated effectiveness. As this requires an estimate by the manager, there is a range of possibilities. To simplify the task, IC Project Planner requires only an estimate of how the manager expects this team will compare to the industry average–expressed as a percentage, either above or below the industry’s norm. In addition to both the manager’s specific knowledge of the team and his or her own past experience, an industry database of more than 1,600 projects coupled with benchmarks of recent projects from the manager’s organization make it straightforward to calibrate expected team performance and generate best-case, worst-case and nominal scenarios.
Numetrics’ approach is inherently different from, but complimentary to, bottom-up planning. Bottom-up project planning itemizes tasks and orders them in time, either in parallel or sequentially. This inherently poses two challenges: trying to catalog every task and estimating the duration of each task. This may work satisfactorily for well-defined tasks and some phases of the project, but it tends to overlook the unexpected and under-represent the more variable periods of project activity. The consequence is poor schedule and resource estimates, which leads to inadequate schedule reliability.
Numetrics’ Project Plan Synthesis solution applies a fact-based approach to estimating project staffing requirements and development cycle time. It models the IC development cycle as a stochastic process, the output of which is based on project’s complexity. Engineering managers provide a high level description of the project that characterizes the chip’s design complexity. The synthesis engine decomposes this information to generate accurate, statistically–based, estimates of the time and effort the average team in the industry would require, from concept phase to release-to-production, to design that chip.
Estimates that Planner generates are statistically centered in the envelope of reality, defined by the execution performance achieved across the industry and within the manager’s own organization on prior projects having similar characteristics. Numetrics’ fact-based approach can be reliably applied earlier in the process than bottom-up planning, and with little effort, to help guide product direction and make better choices. The diagrams show the inputs and outputs of IC Project Planner, as well as the “what-if” simulation paradigm it supports.
IC Project Planner’s output shows what resources are needed and at what stage to help managers plan staffing accurately.
“What-if” Simulation capability within IC Project Planner enables managers to rapidly explore project tradeoffs—chip functionality, staffing and cycle–time—and arrive at the optimal solution:
Using IC Project Planner’s Quickstart capability, managers can generate staffing and schedule estimates even during the very early stages of the planning process–when only initial concepts and rough specs are available. Quickstart brings a high level of confidence into the planning process at the very early stages of the project. With just a high-level description of the chip, Quickstart generates a quantitative assessment of the complexity of the design, as well as an initial estimate of the schedule and corresponding staffing requirements needed to meet the desired target market window. Inputs to Quickstart can be progressively refined as more detail becomes available during the planning process.
Inputs to QuickStart are those factors having the greatest impact on chip development effort. Engineering managers enter parameters such as:
- Process node
- Frequency target and voltage
- Estimated gate count, memory, analog content, I/O count and reuse levels.
This information is processed by the QuickStart complexity calculation engine and then automatically passed to IC Project Planner, which generates estimates of project duration and staffing requirements.
The early estimates that the QuickStart-to-Planner solution enables better decision-making very early in the concept and project planning phases of the IC development cycle. Engineering managers gain quantitative insight into staffing requirements to achieve target schedules. They can also perform “what-if” simulation to explore cycle time vs. Staffing-level vs. Chip complexity tradeoffs. Many of Numetrics’ customers use Quickstart to perform rapid generation of request-for-quote (RFQ) responses, providing their customers’ with estimates of development schedule and non-recurring engineering (NRE) cost in a fast and reliable manner.