By Steven Gary

What keeps people in our industry up at night? If you joined us at the DVCon Industry Leaders panel, moderated by engineer and blogger JL Gray (Cool Verification blog), you heard at least four things:

• We’re struggling to manage the growing complexity
• New tools and IP reuse are not sufficient
• Training next-generation engineers is lacking
• Metrics are needed

Distilling all four, at least to me, yielded a single, fundamental question: How do we as an industry get more productive? Is it the right high-level language? The hot new verification methodology?

Our panel (L-R) John Goodenough, Victor Melamed, Sheela Pillia, Steven Gary, and Jim Crocker (Photo by Joe Hupcey, Cadence Design Systems)

John Goodenough, Worldwide Director Design Technology, ARM, (far left in photo) answered the question with a question:

“How many designers do I have to deploy, train and how do I build this?”

Goodenough said asking about methodology is the wrong question. Asking about workflow is the right question because that’s what affects cost and schedule.

He noted that at ARM, “We’ve stopped talking about interoperability, and we’re now talking about enablement.”

So how does the adoption of new technologies and methods affect your project? How do you figure that out? I noted that engineers are conservative by nature but must push to reach the next level.  After adopting new tools and methodologies, they need a way to quantify how that affects productivity or adds risk to their development schedules.

John said:

“You can’t fix anything you can’t measure, so you have to measure it. It’s hard to measure things; it’s hard to measure intangible things, but you have to take a crack at it.”

Once you begin to measure things, you start to start to see the true workload costs. For example, the industry generally has very high expectations that design reuse will improve productivity simply because those blocks don’t have to be designed from scratch. Yet we’ve measured that and found that below a certain level of design data reuse on an IP block (around 50 percent), the savings from reuse rapidly approach zero. At very low levels, it can cost more to reuse an ip block than to design one from scratch. (We blogged about this paradox last fall: The Design Reuse Paradox).

In the end, it was clear that design and verification today is an enormously complex challenge—from fellow panelist Sheela Pillai’s task at AMD driving complex mixed-signal IP development or Victor Melamed at Ambarella trying to help his colleagues figure out the most effective high-level design language to choose or Jim Crocker from Paradigm Works grappling with engineering training. Quantifying those challenges is the first step toward predictable project outcomes and boosting the industry’s productivity—and getting a good night’s sleep.

P.S. To read more about the panel, please check out Cadence blogger Richard Goering’s post, another interesting perspective that’s definitely worth your time.

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By Ron Collett

We’re gearing up for DVCon (Feb. 22-25) in San Jose and not just because we’re participating in a panel. DVCon (on Twitter, @dvCon), which has emerged as a increasingly important event in recent years, features as keynoter Cadence CEO Lip-bu Tan. His topic gives a new voice to the mounting productivity crisis in semiconductor and system design.

According to an abstract of his talk:

“…the industry must approach the product development process much differently. The classic ‘brute force’ methods cannot scale to support the complexity of today’s SoCs and Systems. These traditional methods result in mounting costs and unpredictable schedules that are detrimental to profitability.”

• Cadence approaches the problem by giving engineers (among many other things) design exploration options that speed the implementation of the physical architecture of a chip.

• Numetrics approaches the problem by helping teams quantify the complexity of their design effort and build reliable project and staffing plans. This is crucial in an era where most IC projects slip schedule significantly.

Our vice president of professional services, Steve Gary, will speak on a panel just after Tan’s, titled “What Keeps You Up at Night?” It’s moderated by JL Gray from Verilabs, who writes the excellent Cool Verification blog; he’s posted a panel preview this week.  Also in the conversation will be John Goodenough from ARM Ltd., Sheela Pillai of Advanced Micro Devices, Inc., Jim Crocker from Paradigm Works, Inc. and Victor Melamed from Ambarella.

There are plenty of things keeping the industry up at night, but I think we’ll hear a lot of excellent ways to overcome the sleeplessness and drive productivity—and the industry—to the next level. Hope to see you there.

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“The complexity of what we have to deliver on exceeds our abilities as experts partly because the volume of knowledge has exceeded what training can possible provide an expert.”

That’s how Atul Gawande, author of “The Checklist Manifesto,” sets up the problem during a podcast interview with Harvard IdeaCast. Gawande is a surgeon and a staff writer for The New Yorker magazine who looks at our ability to be productive in complex situations. His interest, of course, is improving surgical outcomes.
There are, he says, 6,000 drugs and 4,000 medical procedures and increasingly specialized doctors and nurses. We’ve all read stories where surgical implements get left behind in the patient’s body.

I was fascinated by how relevant this is to semiconductor and embedded design. Teams of varying sizes are pulled together on a regular basis—digital specialists, memory specialists, analog designers, software engineers. They’re asked to build increasingly complex systems, with tighter market opportunities, and, like surgery, they find it nearly impossible to plan for the unexpected.

Process, not check marks

Gawande’s checklist approach isn’t about ticking off boxes per se. In the operating room, Gawande devised a two-minute checklist that builds in pauses during surgery to make sure that tasks have been accomplished, that blood is still on hand, and so forth. Perhaps most astonishingly, before the first incision is made, the team takes time to introduce each other by name, so everyone knows everyone else and their expertise and the goal of the operation.

He cites a study done by Geoffrey Smart, who studied decision making among venture capitalists. He compared outcomes of those VCs who, in choosing a entrepreneur, went with their gut (the “art critics”) and those who employed a checklist approach in their selection process (the “airline captains”).

Those who used the checklist approach had far fewer regrets about their selection of managers, and their investments had higher returns.

But the vast majority of VCs are “art critics,” relying on their instincts and experience, rather than the more successful approach.

In system design, many managers rely on their instincts at the beginning of product development to assess how much staff they’ll need and how long the project will take. Clearly something’s wrong because more than 80 percent of semiconductor projects slip schedule.

Learning from the past

It doesn’t have to be this way. Gawande points out that some in the investment banking community rigorously study past investments to understand where failed investments went awry. Sometimes that education leads to adding a check for their next investment checklist: “read all foot notes in the prospectus,” for example.

Successful system-design teams, whether in name or spirit, use similar approaches, and they start with benchmarking themselves against the industry or their own past efforts to understand how to approach their latest product development.

As Gawande implies, it’s often the simplest approaches—and, I’d add, approaches based on facts rather than instinct—that work most effectively.

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Sometimes the simple questions are the most vexing. That hit me this week while participating in a DesignCon panel in Santa Clara, moderated by EDN Executive Editor Ron Wilson.

The title seemed easy enough: “Getting to Design Quality Closure Without Compromising Productivity.”

But really, what IS quality? How do we define it?

My fellow panelist, Camille Kokozaki, president of Design Rivers, quipped “It’s like pornography: you know it when you see it.”

Piyush Sancheti, senior director of business development at Atrenta, came close:

“Quality is meeting the design objectives you have: whether it’s area, power, timing functionality, or, in a broader sense, customer expectations. Productivity is getting there.”

Sancheti then added:

“Being able to measure it (productivity) with tools like Numetrics is important because you want to hit your objectives as fast and effectively as possible.”

Not surprisingly, our panel wrestled with one of the big issues in design quality today: verification. It deeply affects design quality and productivity. Sancheti noted that for some teams, 70 percent of the entire design development is spent on verification.

What I see first hand from customers is they struggle to understand how verification affects their productivity. Some program managers I talk to say:

“I understand the scope of logic design and physical implementation. Verification is an unknown for me. If I give the verification team another two months, they’ll take it, but how do I know that we’re better off?”

So, I think we’re seeing that verification needs to come up with some sort of model of completion so people can move on. And that’s not easy. Our data shows that some companies toggle up the tape-outs as part of a larger verification strategy, but that can hurt overall productivity.

How we fix verification is a broader issue. Do we lean on formal methods at the architectural level as opposed to time- and engineering-consuming test vectors?

For now, our role is to help teams quantify their design effort, properly staff their projects, and understand where they stand with respect to the industry’s best teams. From there they can make fact-based decisions to drive productivity improvements.

That’s our contribution to the broader challenges of verification and design quality, but as we all know, it takes a village (and many future industry panels) to come up with the solution.

(Jeff is Numetrics’ director of professional services and product marketing).

Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

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By Ron Collett

The latest venture capital investment figures are out from PricewaterhouseCoopers’ MoneyTree and the National Venture Capital Association (NVCA). They’re not pretty.

VCs spent just $17.7 billion on 2,795 deals last year. That’s down 36 percent from $27.9 billion in 2008, and it represents the lowest dollar amount and number of investments since 1997.

The chart I pulled together above, based on that data, shows the quarterly VC investment trends for semiconductor companies in just the past three years. Not an encouraging trend line. Total VC investment last year in our industry was $771 million, compared with a peak of $3.4 billion in 2000. What a difference a decade makes.

This realignment of dollars has brought about new expectations from investors and from semiconductor vendors.

Speaking to The Wall Street Journal last week, Bob Ackerman, a venture capitalist at Allegis Capital in Palo Alto, said:

We’re preoccupied by capital efficiency.

Those two words, “capital efficiency,” speak directly to the semiconductor industry’s challenge. This focus on capital efficiency is why semiconductor vendors should be increasingly preoccupied with boosting engineering productivity to get the most from their R&D budget. Lacking an internal fab for differentiation in the fabless era, companies are looking for new ways to gain competitive advantage, and they’re training their sights on their R&D organizations.

The industry’s best-in-class semiconductor IDMs in fact have jumped on this imperative, especially as many of them have shed the last of their owned fabs and now need to compete with fabless companies.

But it works the other way too: Long-time fabless players suddenly find big new competitors that have shed their fabs. They too are looking to boost product-development productivity to stay one step ahead of their new competition.

It’s clear the days of big-time investment are a thing of the past. Today, good companies are those with innovative product ideas; great companies are those that also drive highly productive R&D organizations to get those products completed on predictable schedules and to market ahead of the competition to realize higher returns.

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In December, we were honored to participate in a Design & Reuse panel in Grenoble, France, titled “IP Reuse vs. IP Leverage: What’s the difference and what are the issues?”

Andrea Fortunato, our European director of professional services, represented us and gave an overview of the particular challenges that design reuse brings. He blogged about it right after the panel (Design Reuse: It’s Harder Than it Looks).

Our friends at D&R have just posted an audio Webinar of that panel. It’s definitely worth a listen if you’re designing with cores and trying to take advantage of reusability.

Have you had design reuse challenges recently? If so, feel free to comment on this post to let us know what they were and how you overcame them. Improving productivity in the semiconductor industry is a communal effort!

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I like to catch up on reading during the holidays, and I came across a really interesting exchange on the Becker-Posner blog.

Gary Becker, the University of Chicago economics professor, examined some fresh Bureau of Labor Statistics numbers on productivity (see chart below), which showed productivity is soaring as the nation pulls out of recession.

He wrote:

The fast growth in American productivity toward the end of this serious recession is quite unusual because measured productivity often falls during recessions as companies are stuck with excess capacity of their capital.

His take on the economy’s near-term future, based on this data, was positive. Technology, as it does historically, will be leveraged to advance productivity. His blog partner, Richard Posner, a federal judge and University of Chicago lecturer, was not quite so optimistic:

Posner attributed the productivity gains to “old-fashioned cost cutting spurred not by technological advances but by economic distress.”

The only explanations I have seen offered for the productivity surge is cutting wages and working the workers harder. I have found no suggestion of any technological change that might be responsible for such a large, sudden surge in productivity…Productivity gains that are based merely on adaptations to temporarily depressed economic conditions will be lost when conditions improve. As labor markets tighten, a firm will perforce hire workers who are less productive than the workers it had retained in a slimmed-down workforce during the depression; and so productivity will decline.

I don’t think it’s a zero-sum game. Some rehiring is inevitable but so too is exploiting the advance of technology; smart managers look to technology to advance productivity gains.

We’ve seen our own semiconductor industry begin to roar back to life in recent months, and I can tell you that R&D departments are looking to optimize development efficiency as a new way to differentiate themselves and keep the momentum going. That’s why I think 2010 is the Year of Productivity.

Non-farm labor productivity jumped 6.9% in the second quarter of 2009 and another 8.1 % in the third quarter, surprising some economists.

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(Summary: As the recession’s pain recedes, semiconductor companies have an excellent opportunity to take advantage of the economic crisis to drive productivity improvements throughout their R&D organization.)

The line “never let a serious crisis go to waste” was made famous a year ago by White House chief of Staff Rahm Emanuel, who was speaking to business leaders. For the semiconductor industry emerging from a sharp recession, now is the time to capitalize on the motivation implicit in Emanuel’s quotation.

Consider, first off, the proven benefits that companies get when they take advantage of a recession. A Bain & Company study found that:

• Twice as many companies move from laggards to leaders during a downturn than they do during good times.
• The majority of those companies that take steps to make that move sustained their gains long after business came back.

For those that don’t, the numbers are discouraging:

• One-third of banks and two-fifths of big American industrial companies fell from the first quartile of their industries in the recession of 2001-02, according to a McKinsey study referenced in The Economist.

There’s plenty of advice for companies willing to take advantage of a business slump. Dave Jones and Pierre Loewe, writing on ChiefExecutive.net, advise managers to re-assess “unarticulated” customer needs and redraw their industry ecosystems.

I’d amplify another of their key points: buttress your core competency. Today’s semiconductor industry is a different place than it was before the recession. The search for differentiation in core competencies needs to be focused at product development. This is crucial for fabless companies that don’t have their own manufacturing to create differentiation. But it’s also important for formerly “fabbed” companies making the transition to fabless.

Out with the old?

Some semiconductor companies emerging from this recession will be tempted to apply old templates to new designs. With understandable caution about hiring more engineers in the short-term, the tendency will be to do more with less—to demand more products faster with fewer engineers.

What will happen?

Unrealistic schedules and budget overshoot, for one thing. For another, the urge to crank out more products to take advantage of resuscitated demand will lead to portfolio-management problems.

It doesn’t have to be this way. Productivity improvements and best practices are commonplace in manufacturing; there’s no reason they can’t be employed in R&D. It would be a shame to waste a golden opportunity to exploit this moment in history, and, to finish Emanuel’s quotation, to take the “opportunity to do things you think you could not do before.”

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By Andrea Fortunato

How best can we leverage IP in an era of relentlessly increasing design complexity? That was the question on the table at this week’s IP-ESC 2009 conference here in Grenoble. I was honored to sit on a panel with Jasper Design Automation CEO Kathryn Kranen and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics.

Our CEO, Ron Collett, described the IP situation in a post last week as the design reuse paradox, in that re-using IP is harder than it looks. In fact, there are dangerous consequences for any project leaders who think it’ll be a cakewalk.

During the panel this week, I made the point that most teams underestimate the complexity that the reused IP— adapting a particular block to a new context or adding particular features and then validating it—will add to their project.

This miscalculation is particularly dangerous for derivative designs, whereby the reuse level of their blocks is expected to be significantly high. Executive management loves derivative designs because they’re operating under the assumption that most of the work has already been done on the original design and the derivatives will be easier and deliver higher margin.

Truth and Consequences

But the reality is teams use ever-more IP blocks (including complete functions and sub-systems) on a chip. Underestimating the complexity at the block level is compounded at the chip level, and this creates unrealistic performance expectations from the development teams.

What happens?

• The project schedule slips

• Team members have to be pulled from other on-going projects to bring the project to closure, throwing the predictability of schedule in those other projects into doubt.

What are the consequences?

• The overall market window is reduced and peak time window for product introduction is reduced

• Development cost increases, exploding the project’s initial budget. ROI window is reduced

• Both time to market and ROI are affected!

The ripple effect of underestimating the effort needed to develop, integrate and validate the IP is far-reaching: The resource disruptions delay key projects because resources already involved on other developments are pulled in to salvage one development. The ripples turn into waves that slam the schedule and cause budget over-runs for the whole the project pipeline.

Remediation

There are two major ways to address this situation.

First, fact-based planning at the project’s outset helps avoid this turmoil. By measuring and quantifying project complexity and schedule risk, team leaders can see the gap that might result between their initial effort assumptions and the effort they’ll actually need based on the data. This helps them make fact-backed what-if staffing simulations and create aggressive—yet achievable—schedules.

Second, pick your design battles carefully. Analyzing projects in our extensive industry database, we see that best-in-class design teams show a lower amount of reuse than the average of their segment. This means that those best-in-class projects re-use IP where it is most appropriate to do so—for example in standard functions that don’t bring value add and real differentiation to the final product. But, best-in-class companies leverage their own innovation and fully engage their engineering resources in situations where the performances of specific functions are the key differentiating factors from the competition.

In the end, the key challenge for an IP user is :”Keep the ROI in the Product Development!”

(Andrea Fortunato is director of professional services for Numetrics, based in Grenoble).

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The concept seems simple: The more ip blocks you re-use in an IC or system design, the faster and more productively you’ll get your design done. The ITRS roadmap began identifying the benefits as long ago as 1997, showing the industry could reasonably expect 56,000 gates per designer per year when using large ip blocks (75,000-1 million gates). By 2007 that figure was up to 600,000 gates per designer per year, a tenfold increase.

There’s no doubt design reuse is here to stay. In 2007, a third of all logic was reused design blocks. That’s expected to rise to nearly 50 percent by 2015, according to the ITRS.

The numbers and the theory behind it are encouraging, but reality is much different. Making 30 percent of your design from reused IP blocks doesn’t mean you’re going to be 30 percent more productive at the end of the project. That’s because IC design teams tend to underestimate the work needed to implement the reused IP. This can cause project delays and missed market opportunities.

The challenge is that it’s very difficult to estimate design complexity, especially the impact of reuse. IC design schedules can falter because of the inability to estimate the impact of IP modifications on project effort.

Even a small percentage of reuse can add outsized effort to a development project. For example, if you add one new block of 600,000 gates to a 6 million-gate design, you’re adding 10 percent to the IC but increasing the effort required on the project by 24 percent. Adding 10 percent new circuitry to all blocks in that 6 million-gate design—with 90 percent of each block being re-used—doubles the effort required on the project, even though it increases the IC size by just 10 percent to 6.6 million gates.

This issue will be part of a larger discussion Dec. 1 at IP-ESC 2009 in Grenoble. We were invited to sit on a panel—“IP Reuse vs. IP Leverage: What’s the difference, and what are the issues?”—with Kathryn Kranen, CEO of Jasper Design Automation, and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics. Our director of professional services, Andrea Fortunato, will represent Numetrics.

This is a well-timed panel in my opinion because re-use is an issue that transcends the industry and is crucial for its future. And how we go about optimizing design re-use is crucial to manage today.

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