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    Time-to-Market

    Why They Benchmark Productivity

    by Ron Collett | May 26, 2012 | In Chip Industry, Competition, Competitive Advantage, design complexity, product development, Productivity, Project Planning, R&D, Semiconductor Industry, Team Sizes, Time-to-Market | 1 Comment

    Why do semiconductor organizations benchmark product development productivity? Two reasons. The first is obvious—to determine how their product development competitiveness compares against the industry. R&D prowess is a matter of long-term survival. Second, measuring their productivity enables reliable forecasting of engineering headcount requirements when planning new IC projects. Accurate forecasts equate to both on-time schedule performance and high schedule predictability. It’s a matter of competitive advantage.

    Creating consistently reliable project plans requires a solid grasp of the R&D organization’s development productivity. That’s because productivity dictates how many engineers a project needs to finish on time. Too few engineers and the project slips schedule—a common occurrence. Organizations measuring their productivity calculate exactly how many engineers projects need. [More]

    The Best Laid Plans of Mice and Men

    by Ron Collett | April 18, 2012 | In Chip Industry, design complexity, Functionality, IC Development, Productivity, Project Planning, R&D, Schedule Predictability, schedule slip, Throughput, Time-to-Market | 1 Comment

    Last month on these pages I discussed “The elephant in the corner“–the wholly unrealistic IC development schedule nobody dares openly question. In truth, the situation is often much worse than I described. Usually it isn’t just one elephant in the corner, there’s a herd—a portfolio of projects. In fact, one of the most insidious problems of portfolio management is the failure to adequately verify that project plans are realistic. Because most R&D organizations lack a reliable verification capability, most portfolios end up in chaos—indeed, “the best laid (portfolio) plans of mice and men often go awry.”

    With that in mind, how many chip design projects is your R&D organization currently working on? [More]

    Death of the SoC

    by Ron Collett | May 12, 2011 | In ASICs, Best-in-Class, design complexity, Development Cost, Engineering Labor, Off-shoring, Productivity, Programmable Devices, Schedule Predictability, Semiconductor Industry, SoCs, Systems Industry, systems-on-chips, Team Sizes, Throughput, Time-to-Market, Venture Capital | 1 Comment



    Rumors of the SoC’s impending death have been popping up in the semiconductor and systems industries. Are they exaggerated? Not entirely. A decreasing number of companies are investing in system-on-chips (SoCs). Likewise, the number of concurrent SoC projects that typical R&D organizations can undertake is shrinking. The reason: soaring design cost and poor schedule predictability .That makes SoC development increasingly difficult to justify. But does this foreshadow the SoC’s complete demise? I doubt it, but these factors will surely chase more players from the market and drive greater use of alternative solutions. [More]

     
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