By Ron Collett

In December, we were honored to participate in a Design & Reuse panel in Grenoble, France, titled “IP Reuse vs. IP Leverage: What’s the difference and what are the issues?”

Andrea Fortunato, our European director of professional services, represented us and gave an overview of the particular challenges that design reuse brings. He blogged about it right after the panel (Design Reuse: It’s Harder Than it Looks).

Our friends at D&R have just posted an audio Webinar of that panel. It’s definitely worth a listen if you’re designing with cores and trying to take advantage of reusability.

Have you had design reuse challenges recently? If so, feel free to comment on this post to let us know what they were and how you overcame them. Improving productivity in the semiconductor industry is a communal effort!

(Summary: More than 80 percent of semiconductor projects slip schedule, but we can change this costly reality by introducing a fact-based planning methodology into semiconductor product-development organizations).

By Ron Collett

The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

Here’s a sampling of the presentations:

• “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
• “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
• “Energy Efficient Design at 65nm – What Really Works!”

And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

Wrong.

Projects slip for a number of reasons:

• We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
• We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
• Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

Typical bottom-up reactions to managing such complexity tend to fall into two categories:

• Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
• Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

• Quantified estimates of the chip’s complexity
• The team’s productivity
• A model of the rate at which effort will be expended on the project.

With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

By Ron Collett

Underestimating the complexity of an SOC semiconductor design project is a growing problem in our industry. In an era where SOC projects cost tens of millions of dollars to complete, a week of schedule slip means $1 million or more in lost revenue potential. That’s unacceptable.

That was my main point last week during a panel I participated on that was part of the EE Times SOC Virtual Conference.

Former EE Times EDA Editor Richard Goering, now blogging for Cadence, captured the panel well in a post this week (Are SoC Development Costs Significantly Underestimated?).

To justify the investment in an SoC, Collett said, the available revenue stream must be 10X the development costs. Thus, if an SoC has a $500 million market opportunity, development costs should not exceed $50 million. Today, however, development costs can easily reach $40 to $80 million. Collett noted that 60 percent of this cost is labor and that the major part of the overall development cost is verification.

Richard, with a great comparison, went on to write:

Anyone who has ever been involved in a home remodeling project knows how hard it is to get a reliable estimate up front of how long it will take and how much it will cost. Underestimating time and cost is commonplace. A large SoC design project is far more complex, with many more stakeholders. There is no simple answer to the question of how development costs can be accurately predicted. But there are some ideas about how to lower development costs.

Tensilica CTO Grant Martin weighed in from the IP perspective, Xilinx VP of Product Development Steve Douglass offered the FPGA perspective, and ASIC designer Sven Andersson from Realtime Embedded AB talked about the value of verified IP blocks. It was a great conversation, and you can hear it in archived form by registering for the event.

There’s some additional information about the panel (we tweeted some highlights during the panel) that have been cataloged under the hash tag #eetsoc.And we’ve published a helpful white paper on how to measure IC development productivity in our online library.

Time really is money in the semiconductor industry, and quantifying schedule risk is an excellent way to maximize your engineering investments.

By Ron Collett

I had the pleasure of participating in a great online panel yesterday that was part of the EE Times SOC Virtual Conference, attended live by more than 1,500 people. CTO Grant Martin with Tensilica, product-development Vice President Steve Douglass with Xilinx and ASIC and FPGA designer Sven Andersson of Realtime Embedded AB all contributed to robust discussion of where next-generation design is headed.

I encourage you to listen to panel, which is now archived for the next six months.

My point was pretty straight forward:

• If you misunderstand your semiconductor design project’s true cost, your SOC may be doomed.

Think about it: An SOC design today needs to return 10x its investment. There aren’t a lot of huge end markets that justify SOC projects where the costs and schedule aren’t carefully managed. If the design costs $50 million to $80 million to develop, and there’s only a $200 million market, then the design can’t be justified.

So getting your arms around true development cost is what SOC development is all about.

Summary: Risk to IC development schedules can be minimized by comparing design plan assumptions with a database of historical industry designs and your company’s own history of completed projects to help you determine tradeoffs.

Simply put, schedule risk is the difference between the planned schedule, and the lessons of history. If you plan to finish a design with 20 engineers in 25 weeks, yet industry and corporate comparisons indicate that you need either 27 engineers or to lengthen the schedule to 34 weeks, you have identified schedule risk.

The Numetrics tools can compare your design plan assumptions with all designs in the industry database, or with a subset based on powerful filters, or most powerfully with your own company’s history of completed design projects. If your plan is more aggressive than the results achieved historically, then you risk missing your schedule. High levels of schedule risk disempower your engineers, because the plan feels unrealistic to them. It also creates business risk, especially if schedule is critical. It doesn’t make sense to agree to a plan that requires productivity much greater than you have historically been able to deliver.

On the other hand, it is reasonable to set a stretch goal that is a little better than your historical performance or the industry averages. That’s a stretch goal, and if the team believes it’s feasible, they will work hard to achieve it. This is a point where risk is managed, and the goals are achievable. Everyone likes to outperform their peers, but no one wants to be set up for failure.

By using Numetrics’ tools to analyze schedule risk, you can create a plan that is aggressive, but not so aggressive that it is doomed to fail. Such a plan is good for your team, and good for your business.

Summary: Schedule predictability is the art and science of determining the completion date for your semiconductor IC project, based on a statistical model, validated across multiple designs.

When you plan a project, you are working with incomplete information. Organizational changes, specification changes, technical challenges and more conspire to make it difficult to accurately predict when your new product will be ready.

Schedule predictability is the art and science of determining the completion date for your project, based on a statistical model, validated across multiple designs. The key ingredients are your design’s complexity, coupled with your resource plan. With these two inputs, Numetrics can significantly improve the accuracy of your schedule predictions. One customer went from consistent overruns to accuracy within a few percent on the first designs they modeled in the Numetrics toolset.

How is this possible? The core is the Numetrics ability:

• To understand which factors drive complexity
• To create a normalized characterization of your design that allows comparison with others.

When we compare your proposed design with historical productivity and schedule information, we can statistically determine the expected schedule for your new project. The accuracy of the model is enhanced by our industry database of over 1200 designs, coupled with specific information from your company’s historical project record.

The result is a robust, realistic prediction of the schedule, based on

• Complexity
• Resource availability and
• Historical data.

The value is a greatly enhanced ability to meet your market windows, time and time again.

Summary: Comparing the specifics of your semiconductor design with industry and company history enables insightful what-if scenario analysis to help manage development programs effectively .

During the planning stages for a chip design, there are a number of variables that can be tweaked in the creation of the final product plan. We can reduce or expand the feature set for a new device. We can reduce or extend the schedule. And we can reduce or increase the number of full-time-equivalent (FTE) staff allocated to the project. By manipulating these variables, we can negotiate a plan between the different stakeholders. In some cases, resources are the limiting factor. In others, the schedule is non-negotiable (for example a lot of consumer products must be ready for CES).

Running a lot of plans against all these variables has historically been difficult and time-consuming. In addition, the results have always been subject to arguments because there has been no trusted model to relate complexity, resources and schedule. Numetrics changes all that. By tweaking resource, schedule or feature set (complexity) assumptions, NMX-ERP can rapidly generate graphs that show the feasibility of each plan, and compare it with company and industry norms using their proprietary complexity engine and plan synthesizer.

The speed and defensibility of these analyses lends them great power. It is not rational to assume productivity or schedules that are significantly different from past performance, so any feasible plan must lie close to the lessons of history. There is a cost to adding features, or to shrinking the schedule, or to reducing headcount. The most effective way to negotiate these choices is with the aid of an objective toolset that combines the specifics of your design and plan with industry and company history. The tool is fast enough that you can run tens or even hundreds of plans in minutes or hours. From these scenarios you can then pick the plan that best meets your business goals.

Summary: Realistic semiconductor IC project planning hinges on industry-norm effort, which is the comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

Complexity is a measurement of how difficult it is to complete a design. It’s a measurement based on many attributes of the design, carefully correlated across multiple historical designs. But in order to plan, we need to know the amount of effort it will take to complete a design of a certain complexity. The answer lies in a comparison of the actual productivity achieved by teams across the industry and the actual complexity of their designs.

From this comparison we can calculate the amount of complexity an average designer can implement in a unit of time. Because this is a normative value calculated across the industry, we call it industry norm effort.

We can also make the same calculation for your company—assessing the amount of complexity your designers have historically been able to implement in a unit time. By comparing this with the industry norm, you will get a sense of how your team is doing as compared with the industry.

But the main use of industry norm effort is in conjunction with the complexity data for a proposed design:

• We can accurately and rapidly calculate the total effort required for that design using either your company data, or the industry norm data.

This provides a firm foundation for realistic planning, while still allowing you to set aggressive (but not unrealistic) targets for your team.

Summary: Design complexity can be quantified and communicated in a way that makes IC projects predictable and more productive.

It doesn’t take a rocket scientist to know that the resources and time required to build a chip vary from one design to another. The variation is a function of how difficult the chip will be to build. We measure that and call it complexity.

The hard part, however, is to know which attributes of the design correlate to the effort required to build the chip.

• Is clock speed important?
• What about the number of transistors?
• Re-use?
• Analog and mixed signal?
• Voltage islands?
• Modes?

The list goes on and on. One of the reasons why the NMX-ERP™ software suite accurately forecasts the time and resource requirements for a design is that our engineers, using more than a thousand design projects, have developed a deep understanding of just how hard a given project may be so your engineers can be more productive.

Knowing how to translate chip-design attributes into complexity is the foundation of apples-to-apples comparisons between designs. That’s critical to making sure your latest design can be compared with other industry designs, as well as designs your company has done in the past. After taking in all the complexity factors as chip specifications, Numetrics’ engines can reliably and rapidly calculate the relative complexity of your design, as compared with every other design in our industry database. That’s the foundation upon which all the plan synthesis, what-if scenario analysis, re-planning and root-cause analysis capabilities of NMX-ERP are built.