by Ron Collett | January 26, 2011 | In Best Practices, Competition, IC Development, Project Planning, Schedule Buffers, Schedule Predictability, schedule slip, Semiconductor Industry, Spec Changes | 1 Comment
Poor schedule predictability of IC development projects is the Achilles heel of semiconductor companies. It manifests itself as high schedule slip and is among the most important R&D metrics, measuring how well project schedules reflect reality. Most don’t.
Companies traditionally view schedule slip not as a result of faulty project plans, but rather as a consequence of unforeseeable perturbations occurring during the development process. The picture is incomplete and inaccurate. Slip must also be viewed through the project planning lens, because many events labeled as unforeseeable can be fully contemplated in the project plan with proper modeling. The payoff is big—reliable plans, which is the path to profitability. [More]