Why do semiconductor organizations benchmark product development productivity? Two reasons. The first is obvious—to determine how their product development competitiveness compares against the industry. R&D prowess is a matter of long-term survival. Second, measuring their productivity enables reliable forecasting of engineering headcount requirements when planning new IC projects. Accurate forecasts equate to both on-time schedule performance and high schedule predictability. It’s a matter of competitive advantage.

Creating consistently reliable project plans requires a solid grasp of the R&D organization’s development productivity. That’s because productivity dictates how many engineers a project needs to finish on time. Too few engineers and the project slips schedule—a common occurrence. Organizations measuring their productivity calculate exactly how many engineers projects need. [More]

Last month on these pages I discussed “The elephant in the corner“–the wholly unrealistic IC development schedule nobody dares openly question. In truth, the situation is often much worse than I described. Usually it isn’t just one elephant in the corner, there’s a herd—a portfolio of projects. In fact, one of the most insidious problems of portfolio management is the failure to adequately verify that project plans are realistic. Because most R&D organizations lack a reliable verification capability, most portfolios end up in chaos—indeed, “the best laid (portfolio) plans of mice and men often go awry.”

With that in mind, how many chip design projects is your R&D organization currently working on? [More]

Why do so many IC design teams commit to development schedules they know are not possible to meet? I ask this question because it’s such a common occurrence in the semiconductor industry. (Don’t read this article if you never miss schedules.)

Schedule misses are so common as to be an epidemic. It’s as if unrealistic project plans are part of the DNA of the chip industry.

Design teams are loath to complain too much about pie-in-the-sky plans. That’s because they gain little by raising red flags, even though they end up shouldering much of the blame when projects miss schedule. Moreover, complaints are often met with resistance by some of the organization’s stakeholders. It’s just better to play along with the charade, as it increases the likelihood their project plans will get funded. [More]

Competition among semiconductor companies has become super-heated, and R&D excellence has never been more important to establishing competitive advantage. But how do you know if an organization’s performance is best-in-class, especially that of a competitor? Such accolades are often anecdotal and based heavily on perception, a few unsubstantiated metrics or the halo created by the company’s strong financials. High revenue masks much and distorts even more. [More]

Politics and productivity seem to go hand-in-hand in semiconductor R&D organizations. Perhaps it’s natural. No manager or project team wants the low productivity Scarlet Letter. So it’s hardly surprising that ostensibly poor performers use politics to avoid scrutiny.

But are these so-called low productivity projects really poor performers? In fact, many are not. Quite the opposite in fact—they often have high productivity (although insufficient throughput) but are mistakenly pigeonholed because their crime was a missed schedule. Moreover, schedule overrun usually is not due to low productivity. [More]