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    Project Planning

    The Elephant in the Corner

    by Ron Collett | January 31, 2012 | In Chip Industry, Productivity, Project Planning, R&D, Semiconductor Industry, SoCs, design complexity, schedule slip | 1 Comment

    Why do so many IC design teams commit to development schedules they know are not possible to meet?  I ask this question because it’s such a common occurrence in the semiconductor industry. (Don’t read this article if you never miss schedules.)

    Schedule misses are so common as to be an epidemic. It’s as if unrealistic project plans are part of the DNA of the chip industry.

    Design teams are loath to complain too much about pie-in-the-sky plans. That’s because they gain little by raising red flags, even though they end up shouldering much of the blame when projects miss schedule. Moreover, complaints are often met with resistance by some of the organization’s stakeholders. It’s just better to play along with the charade, as it increases the likelihood their project plans will get funded.

    Once published, such fanciful schedules and resource plans become officially sanctioned propaganda. Just about everybody knows their nonsense, but nobody dares to talk about those big elephants sitting in the corner. At least not until it becomes apparent that the tapeout date will slip—often by months. When it becomes clear that a particular project will badly miss schedule, the organization can collectively and plausibly deny it had any clue that the schedule was unrealistic.

    So who’s part of this conspiracy? The genesis is usually in the engineering organization but quickly works its way to marketing and senior management. It starts in engineering because project managers know that submitting resource plans requesting significantly more engineers than management will approve can be career-limiting. Mid-level managers don’t get promoted for saying they can “do more with more.” Yet, in order to finish projects within the time defined by marketing and customers, project managers know full well that additional resources are critical. I’ve personally seen myriad SoC projects staffed with only half the engineers they actually need to finish on time.

    Does the conspiracy really start with engineering? I think not. More likely it starts with the leadership of the organization—albeit perhaps tacitly. Of course nobody could ever admit to fostering a culture of self-deception, even if unintentional. Likewise, there will never be acknowledgment, tacit or otherwise, of business strategies whose unintended consequence starves projects of resources—even though it’s obvious projects demand more engineering resources to cope with skyrocketing complexity and ever-tightening market windows. I can’t blame management for trying to keep the lid on spending—it’s business. But failure to make the hard decisions about aligning the product portfolio to match resource capacity is fair game for criticism.

    Of course somewhere in this mess sits the unfortunate customer. He’s not savvy to the conspiracy—he never sees the elephant in the corner. He gets a glimpse only when it shows up sitting on his conference room table in the form of the chip vendor’s mea culpa.  Of course during this meeting, the vendor parades out the usual specious suspects that caused the delay, but everyone knows what really happened: A gross mismatch between resources, design complexity and schedule constraint. The consequence of the mismatch was an assumption of development productivity that far exceeded what the design team could realistically achieve. Semiconductor companies should get their R&D houses in order, as customers are increasingly on the hunt for elephants.

    Originally published: http://www.eetimes.com/electronics-blogs/pop-blog/4235164/The-elephant-in-the-corner


    RichMo

    1/24/2012 1:05 PM EST

    I worked for a major semiconductor company for over 14 years. It seems like at least once a year I would get an urgent summons to a scheduling meeting. In order to meet the customer requirement, they had worked the schedule backwards and determined that my tapeout group would have to work over the Christmas holidays. These meetings would usually be held in June or July so I quickly learned just to say “No problem! If you get your design done on time, I will have a team working.” I never had to fulfill my commitment, because the “elephant” was alive and well!

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    RCollett

    1/25/2012 1:49 PM EST

    And who says Christmas doesn’t come in July! Thanks for the comment. Ron

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    zeeglen

    1/24/2012 3:54 PM EST

    Right you are, Ron. I remember a manager who told me outright when I said we would need more time that he had to fit the project within the time and monetary budget or it would never get approved. Schedule slip was the usual result, mostly due to unrealistically short development time dreams.

    Some upper managers could not comprehend that if it takes a cow nine months to produce a calf, one cannot take nine cows and expect the calf in one month. Yes, the math works, but practical development matters rule.

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    RCollett

    1/25/2012 1:50 PM EST

    Having facts data, especially industry data, is the best way to convince skeptics. Thanks for the comment. Ron

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    tb1

    1/24/2012 5:59 PM EST

    I actually once worked for a manager who had very accurate schedules, and we actually met every schedule for board and system delivery. I still have a hard time believing it, since I had never seen this behavior before or since.

    Unfortunately, the software team was managed more conventionally, and the hardware team was always driving them crazy by delivering hardware on time when they weren’t ready for it.

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    RCollett

    1/25/2012 1:51 PM EST

    Maybe that happens more in the systems domain than in semiconductor? Ron

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    jackOfManyTrades

    1/25/2012 3:34 AM EST

    When I was an IC designer, I soon learned that the best time to book a holiday (vacation) was around the tapeout date. That way, there was zero chance of the holiday coinciding with the actual tapeout.

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    RCollett

    1/25/2012 1:52 PM EST

    Too funny! Ron

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    any1

    1/25/2012 9:30 AM EST

    In my experience this deception often starts in marketing. They complain that because engineering is not doing its job fast enough the company is not competitive with its peers and so can’t get enough business to make its sales goals. So then management tells marketing that they can promise better lead times to get those orders and then tells engineering that they have to meet whatever schedule that marketing needs to get the business whether they have the resources to do so or not.

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    R0ckstar

    1/25/2012 6:39 PM EST

    That’s basically it. Schedules are generally DICTATED, not requested. A true schedule would be an exercise in impartial forecasting, guessing when some other design team of which you have no stake – will finish. but for many reasons, most of which have already been mentioned, scheduling a project that you have a personal stake in is inherently problematic. If you really want to know how long a project will take, ask the other department, or start a betting pool then watch what the odds tell you. I guarantee it will be dead on every time!

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    AMSURF

    1/25/2012 5:22 PM EST

    My favorite excuse for the unrealistic schedule is from the Sales or Marketing person who says, “if we don’t deliver it by this date we will lose the socket and be out of the product’s lifecycle!” My response, “let the race to failure begin!”

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    zeeglen

    1/25/2012 6:45 PM EST

    Yup!

    Marketing: “Company X is making a fortune with this. We gotta have something similar in six months or we will miss the Market Window.”

    Engineering response: “Company X has had a whole year to develop this. We need the same. Why the heck didn’t you guys ask for this six months ago?”

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    skal_jp

    1/25/2012 7:35 PM EST

    I remember an argument with my manager:
    - We need to tapeout in 1 week
    - Sorry, with the machine power and license number we have, I need 2 weeks for running all the backannotation simulation
    - Can’t do it in 1 week?
    - Nope.
    - Then only run part of the sim!

    Sim results? There was one pattern with a glitch. Of course in respect this Muphry’s law the glitch was on a pattern I ran after tapeout.

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    zeeglen

    1/25/2012 9:02 PM EST

    So who got blamed for not running the whole test?

    never mind – I can guess

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    t.alex

    1/26/2012 10:21 AM EST

    The customer might be the source of all these in some cases.

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    RCollett

    1/26/2012 3:14 PM EST

    No doubt that customers frequently request/demand an accelerated schedule, which is natural — they’re reacting to the changing competitive forces they themselves are facing. Such requests/demands trigger a chain reaction within the chip supplier’s organization — marketing, engineering, program mgmt., senior mgmt., etc. must respond — and the common response is naturally “yes, we can do it.” That’s not surprising either. Everybody wants/needs to please their customers. However, what often happens is that difficult decisions are avoided. Instead, the organization pretends that somehow ten pounds will fit into a five-pound bag. RC

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    Frank Eory

    1/26/2012 5:06 PM EST

    In my personal experience, this situation has actually improved a lot over the years. Yes, marketing still dictates a market window that must be hit, and the scheduling works backwards from there — from end of qual, to system validation, to first prototypes, fab cycle time, tapeout, verification time, design time, and to product definition and spec writing before design even gets started.

    When that back-to-front scheduling process reveals that design has a negative or unrealistically small positive number of weeks or months to do their job, then the number of choices are very few. If a re-evaluation of the lifetime revenue based on a later market entry still makes business sense, proceed with a new schedule that has the later date. If the resourcing was intentionally lean, add headcount to appropriately resource the project and/or re-define the feature set & scope if a lesser product can still satisfy a segment of the market by meeting the market window.

    If none of those business tests pass, then the right answer is to kill the project and put your engineering resources on a different project where you have better odds of making money. Sales will complain that “we’re going to lose that socket,” but the reality is that you have already lost that socket before you even started the project…because you waited too long to start.

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    RCollett

    1/26/2012 5:29 PM EST

    Frank, what you describe of course is a rationale approach to a challenging situation. However, my observation — based on the Numetrics customers, which is fairly substantial — is that the situation is actually getting worse. It’s because the enormous competition in the semiconductor industry. We need look only at the industry’s M&A activity during the past few years, as well as the companies forced out of business (e.g. the latest being Trident, which recently filed for bankruptcy). The greater the competition, the greater the need for best-in-class management.

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    prabhakar_deosthali

    1/27/2012 6:01 AM EST

    The main reason why schedules are dictated and not requested is that the management thinks that the engineering is always adding a lot of cushion to the timelines to be able to work in a relaxed manner.Mnay of the engineering guys actually do it so that after the squeezing out by the management they get the REAL schedule .

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    RCollett

    1/27/2012 12:57 PM EST

    Prabhakar,

    So you’re saying that in your experience the engineering organization frequently pads the schedule (timeline)?

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    Charlie_Edmondson

    1/27/2012 3:30 PM EST

    There is another side to this problem. A few years ago I was on a project (systems, in this case) where I was the chief hardware designer. My manager was an expert on schedules and budgets, a wiz at anticipating senior managements requests, and an all around good guy. Our hardware team was always on time, on budget, and had a lot of fun.

    The SOFTWARE side, unfortunately, was run by a PHB who was always promising things he couldn’t deliver, was way over budget, always behind on the schedule, and continually complaining he didn’t have enough resources, money, people or time.

    When the phase of the project I was working on came to a close, the company laid off the entire hardware design team, and spent the next year ‘persuading’ the hardware manager to quit. Why? Because he had OBVIOUSLY been featherbedding his budgets and schedules, and not driving his people hard enough. They promoted the software manager… again!

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    peinal

    1/27/2012 3:34 PM EST

    If you think this only occurs in semiconductor design, you’re sadly mistaken. I’ve worked designing HW and SW in military/aero, telecomm, and govt and they all have the same elephant in the room. I once refused to sign a proposal that the govt. required for the preparers. I refused because my initial conservative estimate of 10K hrs was cut to 4K hours on a project that would’ve been 3x more complex than the last one we did (which took 6K hrs). See what I mean?

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    zeeglen

    2/1/2012 6:36 PM EST

    A way around this is to multiply your conservative estimate by four times, then when the bean counters divide by four you get the time you really need.

    Unfortunately the bean counters eventually catch on to this, so you must multiply your next estimate by 8, next by 16…

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    WKetel

    1/27/2012 8:15 PM EST

    My observation has been that sales or marketing will promise anything to get the order, and then engineering and production are blamed when delivery does not happen as promised. This was in the industrial equipment realm, not chip design. Once, a salesman with integrity told us that he would really like the order, but he could not make that delivery. He told us what he could make. Another company claimed no problem with the delivery date, and then wound up being several days later than the supplier that we did not go with. Worse yet, the transducers cost more and were not quite as good. Their catalog got a big red “DO NOT USE” note at that point. I seldom forget a betrayal, and I do take it personally.

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    The Politics of Productivity

    by Ron Collett | March 30, 2011 | In Productivity, Project Planning, R&D, Schedule Predictability, Semiconductor Companies, design complexity | No Comments



    Politics and productivity seem to go hand-in-hand in semiconductor R&D organizations. Perhaps it’s natural. No manager or project team wants the low productivity Scarlet Letter. So it’s hardly surprising that ostensibly poor performers use politics to avoid scrutiny.

    But are these so-called low productivity projects really poor performers? In fact, many are not. Quite the opposite in fact—they often have high productivity (although insufficient throughput) but are mistakenly pigeonholed because their crime was a missed schedule. Moreover, schedule overrun usually is not due to low productivity. [More]

    R&D Predictability: The Path to Profitability

    by Ron Collett | January 26, 2011 | In Best Practices, Competition, IC Development, Project Planning, Schedule Buffers, Schedule Predictability, Semiconductor Industry, Spec Changes, schedule slip | 1 Comment



    Poor schedule predictability of IC development projects is the Achilles heel of semiconductor companies. It manifests itself as high schedule slip and is among the most important R&D metrics, measuring how well project schedules reflect reality. Most don’t.

    Companies traditionally view schedule slip not as a result of faulty project plans, but rather as a consequence of unforeseeable perturbations occurring during the development process. The picture is incomplete and inaccurate. Slip must also be viewed through the project planning lens, because many events labeled as unforeseeable can be fully contemplated in the project plan with proper modeling. The payoff is big—reliable plans, which is the path to profitability. [More]

    Facts and Data vs Heuristics and Hope

    by Numetrics | November 20, 2010 | In Competition, Project Planning, Schedule Predictability, design complexity | 1 Comment

    During the next five years, a great many semiconductor companies will be faced with an increasing number of underperforming business units. Chances are they’ll be selling or spinning them off. Some chip companies, large and small, will disappear altogether. Why? [More]

    How Complex is Your Chip Design?

    by Numetrics | November 11, 2010 | In Data Mining, Project Planning, design complexity | No Comments

    When planning new IC design projects, such as SoCs or complex analog or RF chips, R&D organizations that have a firm grasp on the complexity of implementing the design wield a powerful competitive advantage. Complexity is a measure of engineering difficulty and provides the foundation for reliably estimating engineering resource requirements and development cycle time for projects, which is the essence of good project planning. Can anyone disagree that consistently reliable project plans, which means projects finish on-time and within budget, translate to higher revenue and profits? But how does one get an accurate, quantitative calculation of design complexity? [More]

    The Ripple Effect

    by Ron Collett | August 12, 2010 | In Best Practices, Productivity, Project Planning, Risk Analysis, Schedule Predictability | No Comments

    As a senior product-development manager, you’ve no doubt seen the ripple effect: Your project is humming along and it’s time to add engineers on a crucial part of the design. But wait! The engineers you need are tied up on another project whose schedule has slipped, and they can’t be moved over to yours. What’s worse is when the manager on that project is not sure when they’ll be free.

    You’re frustrated and suddenly stalled on the freeway and what happens in larger organizations is chillingly clear: a chain-reaction crash that creates incredible chaos across the R&D group.

    Missing Schedule

    Air Traffic Control Tower

    Part of the reason so many semiconductor projects miss schedule is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. This is solvable problem.

    Fact-based planning provides the team with data for decision-making—ensuring that projects are staffed properly to meet the demands of the design’s complexity. Estimates of design complexity, project-staffing requirements and development cycle time are generated using empirically calibrated models. This is the heart of Fact-based planning, which is used by top semiconductor companies across the industry.

    Fact-based planning

    • Eases the traditional tension between groups within the enterprise that struggle to communicate in different languages by guiding discussions and strategy with facts and data.
    • Enables predictable revenue streams because it yields accurate schedule estimates, therefore there are no surprise shortfalls in revenue or margins.
    • Leads to predictable schedules, which is crucial in an era when time to market is more important than ever, and companies can’t afford to miss the market upturn.
    • Doesn’t replace bottom-up, detailed planning but complements it.

    Boosting Productivity

    Fact-based planning is essential to an important productivity boosting best practice: seeing the project execution pipeline clearly and managing it centrally. This best practice—and the tooling behind it—rolls up all project plans to generate a picture that shows the total resources consumed by all project plans. With this bird’s-eye view of all project plans, engineering managers can observe where there are shortfalls and over-subscriptions role by role, month by month. This becomes an essential tool for managing the pipeline.

    This isn’t an airbag that protects you in a chain reaction crash. This is a radar system that prevents the crash in the first place and gets everyone to their destinations safely.

    Originally published in EETimes http://www.eetimes.com/discussion/other/4205031/The-ripple-effect

    The Importance of Capital Efficiency

    by Numetrics | January 27, 2010 | In Best Practices, Productivity, Project Planning | No Comments

    VC Funding Chart 2007-2009 copy

    By Ron Collett

    The latest venture capital investment figures are out from PricewaterhouseCoopers’ MoneyTree and the National Venture Capital Association (NVCA). They’re not pretty.

    VCs spent just $17.7 billion on 2,795 deals last year. That’s down 36 percent from $27.9 billion in 2008, and it represents the lowest dollar amount and number of investments since 1997.

    The chart I pulled together above, based on that data, shows the quarterly VC investment trends for semiconductor companies in just the past three years. Not an encouraging trend line. Total VC investment last year in our industry was $771 million, compared with a peak of $3.4 billion in 2000. What a difference a decade makes.

    This realignment of dollars has brought about new expectations from investors and from semiconductor vendors.

    Speaking to The Wall Street Journal last week, Bob Ackerman, a venture capitalist at Allegis Capital in Palo Alto, said:

    We’re preoccupied by capital efficiency.

    Those two words, “capital efficiency,” speak directly to the semiconductor industry’s challenge. This focus on capital efficiency is why semiconductor vendors should be increasingly preoccupied with boosting engineering productivity to get the most from their R&D budget. Lacking an internal fab for differentiation in the fabless era, companies are looking for new ways to gain competitive advantage, and they’re training their sights on their R&D organizations.

    The industry’s best-in-class semiconductor IDMs in fact have jumped on this imperative, especially as many of them have shed the last of their owned fabs and now need to compete with fabless companies.

    But it works the other way too: Long-time fabless players suddenly find big new competitors that have shed their fabs. They too are looking to boost product-development productivity to stay one step ahead of their new competition.

    It’s clear the days of big-time investment are a thing of the past. Today, good companies are those with innovative product ideas; great companies are those that also drive highly productive R&D organizations to get those products completed on predictable schedules and to market ahead of the competition to realize higher returns.

    Design Reuse: It’s Harder Than it Looks

    by Numetrics | December 3, 2009 | In Best Practices, Productivity, Project Planning | 1 Comment

    By Andrea Fortunato

    How best can we leverage IP in an era of relentlessly increasing design complexity? That was the question on the table at this week’s IP-ESC 2009 conference here in Grenoble. I was honored to sit on a panel with Jasper Design Automation CEO Kathryn Kranen and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics.

    Our CEO, Ron Collett, described the IP situation in a post last week as the design reuse paradox, in that re-using IP is harder than it looks. In fact, there are dangerous consequences for any project leaders who think it’ll be a cakewalk.

    During the panel this week, I made the point that most teams underestimate the complexity that the reused IP— adapting a particular block to a new context or adding particular features and then validating it—will add to their project.

    This miscalculation is particularly dangerous for derivative designs, whereby the reuse level of their blocks is expected to be significantly high. Executive management loves derivative designs because they’re operating under the assumption that most of the work has already been done on the original design and the derivatives will be easier and deliver higher margin.

    Truth and Consequences

    But the reality is teams use ever-more IP blocks (including complete functions and sub-systems) on a chip. Underestimating the complexity at the block level is compounded at the chip level, and this creates unrealistic performance expectations from the development teams.

    What happens?

    • The project schedule slips

    • Team members have to be pulled from other on-going projects to bring the project to closure, throwing the predictability of schedule in those other projects into doubt.

    What are the consequences?

    • The overall market window is reduced and peak time window for product introduction is reduced

    • Development cost increases, exploding the project’s initial budget. ROI window is reduced

    • Both time to market and ROI are affected!

    The ripple effect of underestimating the effort needed to develop, integrate and validate the IP is far-reaching: The resource disruptions delay key projects because resources already involved on other developments are pulled in to salvage one development. The ripples turn into waves that slam the schedule and cause budget over-runs for the whole the project pipeline.

    Remediation

    There are two major ways to address this situation.

    First, fact-based planning at the project’s outset helps avoid this turmoil. By measuring and quantifying project complexity and schedule risk, team leaders can see the gap that might result between their initial effort assumptions and the effort they’ll actually need based on the data. This helps them make fact-backed what-if staffing simulations and create aggressive—yet achievable—schedules.

    Second, pick your design battles carefully. Analyzing projects in our extensive industry database, we see that best-in-class design teams show a lower amount of reuse than the average of their segment. This means that those best-in-class projects re-use IP where it is most appropriate to do so—for example in standard functions that don’t bring value add and real differentiation to the final product. But, best-in-class companies leverage their own innovation and fully engage their engineering resources in situations where the performances of specific functions are the key differentiating factors from the competition.

    In the end, the key challenge for an IP user is :”Keep the ROI in the Product Development!”

    (Andrea Fortunato is director of professional services for Numetrics, based in Grenoble).

    Productivity, Predictability and other Burning Questions

    by Numetrics | November 4, 2009 | In Best Practices, Productivity, Project Planning | No Comments

    By Alex Silbey

    (Summary: We inevitably get questions about Numetrics’ technology after webinars or live event presentations, and we’d like to share some of them in the spirit of helping you understand more about our products and solutions. Here are answers to several recent questions in the virtual mail bag).

    Q: How do you define productivity?

    A: We calculate complexity of the project and we divide the complexity units by total number of person weeks required to get that product out to volume production. That quotient gives you the productivity number. The typical range is 500 on the low end for a large team to 3000 for a small team.

    There’s another measure, which is throughput, and throughput is complexity units per week. That’s a measure of normalized cycle team. Productivity is efficiency of the team and higher number is better.

    Q: I’ve heard that in some sectors productivity decreases as team size increases. Is this true in semiconductor product development?

    A: It’s a universal effect across pretty much any activity that has to do with building things. When you build larger teams, each person is doing a smaller and smaller slice of the overall work. More work has to be split apart and then put back together. Bigger teams equal more meetings and more management required. It’s universal and it’s inevitable. With the Numetrics approach, you can minimize this effect—decreasing productivity curve is flatter than it would otherwise be.

    Q: It’s impossible to predict in a design project how many times customer requirements will change, when your EDA tools go buggy or if a key contributor leaves the team. So how do you quantify schedule risk with so many unpredictable variables?

    A: The simple answer is our tools don’t predict things. You have a draw a line between statistical analysis and a crystal ball.

    What Numetrics’ tools do is take your inputs of design parameters and measure them against the history of more than 1,500 design projects over eight generations of technology evolution (here’s a link to a demo of our tools). Using the data from those hundreds and hundreds of designs, this builds in realistic effort required to deal with those issues. It’s a way of contingency planning.

    Think of it like yield modeling. You know that on each wafer a certain number of dice will fall out. Yield modeling doesn’t tell you which particle is going to hit which die and where. But they give you an accurate assessment of how your design will yield. Numetrics is like a yield model for project plans. It’s saying there’s a certain probability that if you’re going to try to achieve these targets, given what you’ve input you’re going to fail.

    It allows you to make a quantitative assessments. It’s a probability model. It’s not a crystal ball.

    Q: How does the complexity calculation model handle predictions for newer nodes, such as 45 and 32nm?

    A: Numetrics’ IC Industry Database has collected information for eight technology generations. The technology shifts from one generation to another have been observed before. And what we’ve observed is that early users of technology nodes face considerably more complexity than later users of the same node, once the models and such are more stable. The equation has calibrated this effect which repeats from generation to generation. We’ve been able to model what the effect of the extra technology of a new node will be on a new design.

    Q: Can your tools get data from existing sources or do I have to input it manually?

    A: We’re dealing with milestones, staffing information and complexity information. Typically this information is copy-pasted from existing sources or customers are using XML import to get data into our tools.

    (Alex is Numetrics’ director of professional services).

    Why Most Semiconductor Design Projects Slip Schedule

    by Numetrics | October 19, 2009 | In Productivity, Project Planning, Schedule Predictability | No Comments

    (Summary: More than 80 percent of semiconductor projects slip schedule, but we can change this costly reality by introducing a fact-based planning methodology into semiconductor product-development organizations).

    By Ron Collett

    The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

    Here’s a sampling of the presentations:

    • “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
    • “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
    • “Energy Efficient Design at 65nm – What Really Works!”

    And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

    Schedule Slip Bar Graph

    Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

    Wrong.

    Projects slip for a number of reasons:

    • We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
    • We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
    • Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

    Typical bottom-up reactions to managing such complexity tend to fall into two categories:

    • Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
    • Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

    Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

    • Quantified estimates of the chip’s complexity
    • The team’s productivity
    • A model of the rate at which effort will be expended on the project.

    With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

    More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

     
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