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    Productivity

    The Elephant in the Corner

    by Ron Collett | January 31, 2012 | In Chip Industry, Productivity, Project Planning, R&D, Semiconductor Industry, SoCs, design complexity, schedule slip | 1 Comment

    Why do so many IC design teams commit to development schedules they know are not possible to meet?  I ask this question because it’s such a common occurrence in the semiconductor industry. (Don’t read this article if you never miss schedules.)

    Schedule misses are so common as to be an epidemic. It’s as if unrealistic project plans are part of the DNA of the chip industry.

    Design teams are loath to complain too much about pie-in-the-sky plans. That’s because they gain little by raising red flags, even though they end up shouldering much of the blame when projects miss schedule. Moreover, complaints are often met with resistance by some of the organization’s stakeholders. It’s just better to play along with the charade, as it increases the likelihood their project plans will get funded.

    Once published, such fanciful schedules and resource plans become officially sanctioned propaganda. Just about everybody knows their nonsense, but nobody dares to talk about those big elephants sitting in the corner. At least not until it becomes apparent that the tapeout date will slip—often by months. When it becomes clear that a particular project will badly miss schedule, the organization can collectively and plausibly deny it had any clue that the schedule was unrealistic.

    So who’s part of this conspiracy? The genesis is usually in the engineering organization but quickly works its way to marketing and senior management. It starts in engineering because project managers know that submitting resource plans requesting significantly more engineers than management will approve can be career-limiting. Mid-level managers don’t get promoted for saying they can “do more with more.” Yet, in order to finish projects within the time defined by marketing and customers, project managers know full well that additional resources are critical. I’ve personally seen myriad SoC projects staffed with only half the engineers they actually need to finish on time.

    Does the conspiracy really start with engineering? I think not. More likely it starts with the leadership of the organization—albeit perhaps tacitly. Of course nobody could ever admit to fostering a culture of self-deception, even if unintentional. Likewise, there will never be acknowledgment, tacit or otherwise, of business strategies whose unintended consequence starves projects of resources—even though it’s obvious projects demand more engineering resources to cope with skyrocketing complexity and ever-tightening market windows. I can’t blame management for trying to keep the lid on spending—it’s business. But failure to make the hard decisions about aligning the product portfolio to match resource capacity is fair game for criticism.

    Of course somewhere in this mess sits the unfortunate customer. He’s not savvy to the conspiracy—he never sees the elephant in the corner. He gets a glimpse only when it shows up sitting on his conference room table in the form of the chip vendor’s mea culpa.  Of course during this meeting, the vendor parades out the usual specious suspects that caused the delay, but everyone knows what really happened: A gross mismatch between resources, design complexity and schedule constraint. The consequence of the mismatch was an assumption of development productivity that far exceeded what the design team could realistically achieve. Semiconductor companies should get their R&D houses in order, as customers are increasingly on the hunt for elephants.

    Originally published: http://www.eetimes.com/electronics-blogs/pop-blog/4235164/The-elephant-in-the-corner


    RichMo

    1/24/2012 1:05 PM EST

    I worked for a major semiconductor company for over 14 years. It seems like at least once a year I would get an urgent summons to a scheduling meeting. In order to meet the customer requirement, they had worked the schedule backwards and determined that my tapeout group would have to work over the Christmas holidays. These meetings would usually be held in June or July so I quickly learned just to say “No problem! If you get your design done on time, I will have a team working.” I never had to fulfill my commitment, because the “elephant” was alive and well!

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    RCollett

    1/25/2012 1:49 PM EST

    And who says Christmas doesn’t come in July! Thanks for the comment. Ron

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    zeeglen

    1/24/2012 3:54 PM EST

    Right you are, Ron. I remember a manager who told me outright when I said we would need more time that he had to fit the project within the time and monetary budget or it would never get approved. Schedule slip was the usual result, mostly due to unrealistically short development time dreams.

    Some upper managers could not comprehend that if it takes a cow nine months to produce a calf, one cannot take nine cows and expect the calf in one month. Yes, the math works, but practical development matters rule.

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    RCollett

    1/25/2012 1:50 PM EST

    Having facts data, especially industry data, is the best way to convince skeptics. Thanks for the comment. Ron

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    tb1

    1/24/2012 5:59 PM EST

    I actually once worked for a manager who had very accurate schedules, and we actually met every schedule for board and system delivery. I still have a hard time believing it, since I had never seen this behavior before or since.

    Unfortunately, the software team was managed more conventionally, and the hardware team was always driving them crazy by delivering hardware on time when they weren’t ready for it.

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    RCollett

    1/25/2012 1:51 PM EST

    Maybe that happens more in the systems domain than in semiconductor? Ron

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    jackOfManyTrades

    1/25/2012 3:34 AM EST

    When I was an IC designer, I soon learned that the best time to book a holiday (vacation) was around the tapeout date. That way, there was zero chance of the holiday coinciding with the actual tapeout.

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    RCollett

    1/25/2012 1:52 PM EST

    Too funny! Ron

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    any1

    1/25/2012 9:30 AM EST

    In my experience this deception often starts in marketing. They complain that because engineering is not doing its job fast enough the company is not competitive with its peers and so can’t get enough business to make its sales goals. So then management tells marketing that they can promise better lead times to get those orders and then tells engineering that they have to meet whatever schedule that marketing needs to get the business whether they have the resources to do so or not.

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    R0ckstar

    1/25/2012 6:39 PM EST

    That’s basically it. Schedules are generally DICTATED, not requested. A true schedule would be an exercise in impartial forecasting, guessing when some other design team of which you have no stake – will finish. but for many reasons, most of which have already been mentioned, scheduling a project that you have a personal stake in is inherently problematic. If you really want to know how long a project will take, ask the other department, or start a betting pool then watch what the odds tell you. I guarantee it will be dead on every time!

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    AMSURF

    1/25/2012 5:22 PM EST

    My favorite excuse for the unrealistic schedule is from the Sales or Marketing person who says, “if we don’t deliver it by this date we will lose the socket and be out of the product’s lifecycle!” My response, “let the race to failure begin!”

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    zeeglen

    1/25/2012 6:45 PM EST

    Yup!

    Marketing: “Company X is making a fortune with this. We gotta have something similar in six months or we will miss the Market Window.”

    Engineering response: “Company X has had a whole year to develop this. We need the same. Why the heck didn’t you guys ask for this six months ago?”

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    skal_jp

    1/25/2012 7:35 PM EST

    I remember an argument with my manager:
    - We need to tapeout in 1 week
    - Sorry, with the machine power and license number we have, I need 2 weeks for running all the backannotation simulation
    - Can’t do it in 1 week?
    - Nope.
    - Then only run part of the sim!

    Sim results? There was one pattern with a glitch. Of course in respect this Muphry’s law the glitch was on a pattern I ran after tapeout.

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    zeeglen

    1/25/2012 9:02 PM EST

    So who got blamed for not running the whole test?

    never mind – I can guess

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    t.alex

    1/26/2012 10:21 AM EST

    The customer might be the source of all these in some cases.

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    RCollett

    1/26/2012 3:14 PM EST

    No doubt that customers frequently request/demand an accelerated schedule, which is natural — they’re reacting to the changing competitive forces they themselves are facing. Such requests/demands trigger a chain reaction within the chip supplier’s organization — marketing, engineering, program mgmt., senior mgmt., etc. must respond — and the common response is naturally “yes, we can do it.” That’s not surprising either. Everybody wants/needs to please their customers. However, what often happens is that difficult decisions are avoided. Instead, the organization pretends that somehow ten pounds will fit into a five-pound bag. RC

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    Frank Eory

    1/26/2012 5:06 PM EST

    In my personal experience, this situation has actually improved a lot over the years. Yes, marketing still dictates a market window that must be hit, and the scheduling works backwards from there — from end of qual, to system validation, to first prototypes, fab cycle time, tapeout, verification time, design time, and to product definition and spec writing before design even gets started.

    When that back-to-front scheduling process reveals that design has a negative or unrealistically small positive number of weeks or months to do their job, then the number of choices are very few. If a re-evaluation of the lifetime revenue based on a later market entry still makes business sense, proceed with a new schedule that has the later date. If the resourcing was intentionally lean, add headcount to appropriately resource the project and/or re-define the feature set & scope if a lesser product can still satisfy a segment of the market by meeting the market window.

    If none of those business tests pass, then the right answer is to kill the project and put your engineering resources on a different project where you have better odds of making money. Sales will complain that “we’re going to lose that socket,” but the reality is that you have already lost that socket before you even started the project…because you waited too long to start.

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    RCollett

    1/26/2012 5:29 PM EST

    Frank, what you describe of course is a rationale approach to a challenging situation. However, my observation — based on the Numetrics customers, which is fairly substantial — is that the situation is actually getting worse. It’s because the enormous competition in the semiconductor industry. We need look only at the industry’s M&A activity during the past few years, as well as the companies forced out of business (e.g. the latest being Trident, which recently filed for bankruptcy). The greater the competition, the greater the need for best-in-class management.

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    prabhakar_deosthali

    1/27/2012 6:01 AM EST

    The main reason why schedules are dictated and not requested is that the management thinks that the engineering is always adding a lot of cushion to the timelines to be able to work in a relaxed manner.Mnay of the engineering guys actually do it so that after the squeezing out by the management they get the REAL schedule .

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    RCollett

    1/27/2012 12:57 PM EST

    Prabhakar,

    So you’re saying that in your experience the engineering organization frequently pads the schedule (timeline)?

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    Charlie_Edmondson

    1/27/2012 3:30 PM EST

    There is another side to this problem. A few years ago I was on a project (systems, in this case) where I was the chief hardware designer. My manager was an expert on schedules and budgets, a wiz at anticipating senior managements requests, and an all around good guy. Our hardware team was always on time, on budget, and had a lot of fun.

    The SOFTWARE side, unfortunately, was run by a PHB who was always promising things he couldn’t deliver, was way over budget, always behind on the schedule, and continually complaining he didn’t have enough resources, money, people or time.

    When the phase of the project I was working on came to a close, the company laid off the entire hardware design team, and spent the next year ‘persuading’ the hardware manager to quit. Why? Because he had OBVIOUSLY been featherbedding his budgets and schedules, and not driving his people hard enough. They promoted the software manager… again!

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    peinal

    1/27/2012 3:34 PM EST

    If you think this only occurs in semiconductor design, you’re sadly mistaken. I’ve worked designing HW and SW in military/aero, telecomm, and govt and they all have the same elephant in the room. I once refused to sign a proposal that the govt. required for the preparers. I refused because my initial conservative estimate of 10K hrs was cut to 4K hours on a project that would’ve been 3x more complex than the last one we did (which took 6K hrs). See what I mean?

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    zeeglen

    2/1/2012 6:36 PM EST

    A way around this is to multiply your conservative estimate by four times, then when the bean counters divide by four you get the time you really need.

    Unfortunately the bean counters eventually catch on to this, so you must multiply your next estimate by 8, next by 16…

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    WKetel

    1/27/2012 8:15 PM EST

    My observation has been that sales or marketing will promise anything to get the order, and then engineering and production are blamed when delivery does not happen as promised. This was in the industrial equipment realm, not chip design. Once, a salesman with integrity told us that he would really like the order, but he could not make that delivery. He told us what he could make. Another company claimed no problem with the delivery date, and then wound up being several days later than the supplier that we did not go with. Worse yet, the transducers cost more and were not quite as good. Their catalog got a big red “DO NOT USE” note at that point. I seldom forget a betrayal, and I do take it personally.

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    End of the Free Ride

    by Ron Collett | October 25, 2011 | In IC Development, Off-shoring, Productivity, ROI, Schedule Predictability, Semiconductor Companies, SoCs, product development | No Comments

    According to Pagemill Partners, a well-known Silicon Valley venture capital (VC) firm, the number of semiconductor companies spawned with VC funding has been steadily declining for nearly a decade. In 2003, VCs gave life to 63 new chip companies. Last year the number was 13. It’s a trend that promises to reshape the semiconductor industry. (Note: the figures reflect companies formed in North America, Europe and Israel.)

    Established chip companies planning to expand via acquisitions should take notice. [More]

    The Realities of IP Reuse

    by Ron Collett | August 24, 2011 | In IP reuse, Productivity, Schedule Predictability, Throughput, schedule slip | 1 Comment

    Long touted as a silver bullet, IP reuse often fails to live up to expectations when it comes to increasing semiconductor R&D productivity and throughput . That’s because most IC development teams fail to recognize a critical non-linear relationship exists between the amount of circuitry they modify or “improve” in pre-existing IP blocks and the effort the engineering team expends in making those modified blocks operate properly in the target IC. Bottom line: small changes can have a disproportionate impact on project effort. Not being fully cognizant of the specifics of this non-linear behavior is a common trap into which myriad engineering teams unwittingly fall. [More]

    Does EDA Matter Anymore?

    by Ron Collett | June 29, 2011 | In IC Development, Productivity, Semiconductor Companies, design complexity, product development | 1 Comment



    Of course electronic design automation (EDA) matters! It’s indispensible to chip design. However, the more important question is whether EDA is keeping pace with increasing IC design complexity. In most cases, the answer is no. Design complexity is increasing much faster than productivity. How do I know? Average development team size continues to grow.

    So where does that put EDA? Perhaps the best place to look is the Design Automation Conference held a few weeks ago in San Diego. The venerable 48-year-old show played host to nearly 200 vendors, staged myriad panel sessions and technical papers, and attracted thousands of attendees. But as far as I could tell there were no earth-shattering tool breakthroughs portending to reverse the tide. Maybe you saw something I missed—let me know. Naturally, vendors announced plenty of new products, many of which will undoubtedly boost productivity. But none are likely to obviate the need for ever-larger teams, which is the current prescription for declining relative-productivity. [More]

    Death of the SoC

    by Ron Collett | May 12, 2011 | In ASICs, Best-in-Class, Development Cost, Engineering Labor, Off-shoring, Productivity, Programmable Devices, Schedule Predictability, Semiconductor Industry, SoCs, Systems Industry, Team Sizes, Throughput, Time-to-Market, Venture Capital, design complexity, systems-on-chips | 1 Comment



    Rumors of the SoC’s impending death have been popping up in the semiconductor and systems industries. Are they exaggerated? Not entirely. A decreasing number of companies are investing in system-on-chips (SoCs). Likewise, the number of concurrent SoC projects that typical R&D organizations can undertake is shrinking. The reason: soaring design cost and poor schedule predictability .That makes SoC development increasingly difficult to justify. But does this foreshadow the SoC’s complete demise? I doubt it, but these factors will surely chase more players from the market and drive greater use of alternative solutions. [More]

    In Search of Best-In-Class R&D Organizations

    by Ron Collett | April 15, 2011 | In Best-in-Class, Competition, Competitive Advantage, Metrics, Productivity, R&D, design complexity | 1 Comment

    Competition among semiconductor companies has become super-heated, and R&D excellence has never been more important to establishing competitive advantage. But how do you know if an organization’s performance is best-in-class, especially that of a competitor? Such accolades are often anecdotal and based heavily on perception, a few unsubstantiated metrics or the halo created by the company’s strong financials. High revenue masks much and distorts even more. [More]

    The Politics of Productivity

    by Ron Collett | March 30, 2011 | In Productivity, Project Planning, R&D, Schedule Predictability, Semiconductor Companies, design complexity | No Comments



    Politics and productivity seem to go hand-in-hand in semiconductor R&D organizations. Perhaps it’s natural. No manager or project team wants the low productivity Scarlet Letter. So it’s hardly surprising that ostensibly poor performers use politics to avoid scrutiny.

    But are these so-called low productivity projects really poor performers? In fact, many are not. Quite the opposite in fact—they often have high productivity (although insufficient throughput) but are mistakenly pigeonholed because their crime was a missed schedule. Moreover, schedule overrun usually is not due to low productivity. [More]

    Optimal Team Sizes for Chip Projects

    by Ron Collett | March 3, 2011 | In Best-in-Class, Competitive Advantage, Diminishing Returns, Meeting Schedule Targets, Productivity, ROI, Throughput, design complexity, schedule slip | No Comments



    What’s the optimal team size for a given IC design project? It’s a question I hear often from engineering managers and senior executives. What they’re actually asking is whether they’re over-staffing projects and therefore wasting resources. Implicitly, they’re also asking “what’s the fewest number of engineers I can put on a given project and still finish on time?” They’re important questions directly impacting R&D ROI. [More]

    The Most Important R&D Performance Metrics

    by Ron Collett | January 15, 2011 | In Best-in-Class, Increasing Profit, Increasing Revenue, Metrics, PRTM, Performance Metrics, Productivity, Resource Leakage, Semiconductor Companies, Throughput, Utilization, product development | 1 Comment



    Engineering utilization, productivity and throughput are among the most important metrics for measuring R&D performance. If you want to improve your R&D capability, focus on these three metrics.

    Productivity and utilization directly determine throughput, and throughput is the most important of all R&D performance metrics. It measures the rate at which an R&D team develops production-ready products. The higher the productivity and utilization, the higher the R&D throughput. Higher throughput means the R&D team churns out more products in a given period of time. That usually translates to revenue and profits— assuming the rest of the enterprise pulls its weight. Big assumption, right? [More]

    Throughput, Not Productivity, is What Matters

    by Ron Collett | December 16, 2010 | In Productivity | 1 Comment

    Discussions about R&D return-on-investment (RoI) among semiconductor industry executives often turn to engineering productivity. They’re often surprised when I assert that productivity isn’t that important—at least as far as R&D performance metrics are concerned. A far more important metric is engineering throughput. [More]

     
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