The Best Laid Plans of Mice and Men
by Ron Collett | April 18, 2012 | In Chip Industry, design complexity, Functionality, IC Development, Productivity, Project Planning, R&D, Schedule Predictability, schedule slip, Throughput, Time-to-Market | 1 Comment
Last month on these pages I discussed “The elephant in the corner“–the wholly unrealistic IC development schedule nobody dares openly question. In truth, the situation is often much worse than I described. Usually it isn’t just one elephant in the corner, there’s a herd—a portfolio of projects. In fact, one of the most insidious problems of portfolio management is the failure to adequately verify that project plans are realistic. Because most R&D organizations lack a reliable verification capability, most portfolios end up in chaos—indeed, “the best laid (portfolio) plans of mice and men often go awry.”
With that in mind, how many chip design projects is your R&D organization currently working on? [More]
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