By Steven Gary

What keeps people in our industry up at night? If you joined us at the DVCon Industry Leaders panel, moderated by engineer and blogger JL Gray (Cool Verification blog), you heard at least four things:

• We’re struggling to manage the growing complexity
• New tools and IP reuse are not sufficient
• Training next-generation engineers is lacking
• Metrics are needed

Distilling all four, at least to me, yielded a single, fundamental question: How do we as an industry get more productive? Is it the right high-level language? The hot new verification methodology?

Our panel (L-R) John Goodenough, Victor Melamed, Sheela Pillia, Steven Gary, and Jim Crocker (Photo by Joe Hupcey, Cadence Design Systems)

John Goodenough, Worldwide Director Design Technology, ARM, (far left in photo) answered the question with a question:

“How many designers do I have to deploy, train and how do I build this?”

Goodenough said asking about methodology is the wrong question. Asking about workflow is the right question because that’s what affects cost and schedule.

He noted that at ARM, “We’ve stopped talking about interoperability, and we’re now talking about enablement.”

So how does the adoption of new technologies and methods affect your project? How do you figure that out? I noted that engineers are conservative by nature but must push to reach the next level.  After adopting new tools and methodologies, they need a way to quantify how that affects productivity or adds risk to their development schedules.

John said:

“You can’t fix anything you can’t measure, so you have to measure it. It’s hard to measure things; it’s hard to measure intangible things, but you have to take a crack at it.”

Once you begin to measure things, you start to start to see the true workload costs. For example, the industry generally has very high expectations that design reuse will improve productivity simply because those blocks don’t have to be designed from scratch. Yet we’ve measured that and found that below a certain level of design data reuse on an IP block (around 50 percent), the savings from reuse rapidly approach zero. At very low levels, it can cost more to reuse an ip block than to design one from scratch. (We blogged about this paradox last fall: The Design Reuse Paradox).

In the end, it was clear that design and verification today is an enormously complex challenge—from fellow panelist Sheela Pillai’s task at AMD driving complex mixed-signal IP development or Victor Melamed at Ambarella trying to help his colleagues figure out the most effective high-level design language to choose or Jim Crocker from Paradigm Works grappling with engineering training. Quantifying those challenges is the first step toward predictable project outcomes and boosting the industry’s productivity—and getting a good night’s sleep.

P.S. To read more about the panel, please check out Cadence blogger Richard Goering’s post, another interesting perspective that’s definitely worth your time.