By Ron Collett

We’re gearing up for DVCon (Feb. 22-25) in San Jose and not just because we’re participating in a panel. DVCon (on Twitter, @dvCon), which has emerged as a increasingly important event in recent years, features as keynoter Cadence CEO Lip-bu Tan. His topic gives a new voice to the mounting productivity crisis in semiconductor and system design.

According to an abstract of his talk:

“…the industry must approach the product development process much differently. The classic ‘brute force’ methods cannot scale to support the complexity of today’s SoCs and Systems. These traditional methods result in mounting costs and unpredictable schedules that are detrimental to profitability.”

• Cadence approaches the problem by giving engineers (among many other things) design exploration options that speed the implementation of the physical architecture of a chip.

• Numetrics approaches the problem by helping teams quantify the complexity of their design effort and build reliable project and staffing plans. This is crucial in an era where most IC projects slip schedule significantly.

Our vice president of professional services, Steve Gary, will speak on a panel just after Tan’s, titled “What Keeps You Up at Night?” It’s moderated by JL Gray from Verilabs, who writes the excellent Cool Verification blog; he’s posted a panel preview this week.  Also in the conversation will be John Goodenough from ARM Ltd., Sheela Pillai of Advanced Micro Devices, Inc., Jim Crocker from Paradigm Works, Inc. and Victor Melamed from Ambarella.

There are plenty of things keeping the industry up at night, but I think we’ll hear a lot of excellent ways to overcome the sleeplessness and drive productivity—and the industry—to the next level. Hope to see you there.

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“The complexity of what we have to deliver on exceeds our abilities as experts partly because the volume of knowledge has exceeded what training can possible provide an expert.”

By Ron Collett

That’s how Atul Gawande, author of “The Checklist Manifesto,” sets up the problem during a podcast interview with Harvard IdeaCast. Gawande is a surgeon and a staff writer for The New Yorker magazine who looks at our ability to be productive in complex situations. His interest, of course, is improving surgical outcomes.
There are, he says, 6,000 drugs and 4,000 medical procedures and increasingly specialized doctors and nurses. We’ve all read stories where surgical implements get left behind in the patient’s body.

I was fascinated by how relevant this is to semiconductor and embedded design. Teams of varying sizes are pulled together on a regular basis—digital specialists, memory specialists, analog designers, software engineers. They’re asked to build increasingly complex systems, with tighter market opportunities, and, like surgery, they find it nearly impossible to plan for the unexpected.

Process, not check marks

Gawande’s checklist approach isn’t about ticking off boxes per se. In the operating room, Gawande devised a two-minute checklist that builds in pauses during surgery to make sure that tasks have been accomplished, that blood is still on hand, and so forth. Perhaps most astonishingly, before the first incision is made, the team takes time to introduce each other by name, so everyone knows everyone else and their expertise and the goal of the operation.

He cites a study done by Geoffrey Smart, who studied decision making among venture capitalists. He compared outcomes of those VCs who, in choosing a entrepreneur, went with their gut (the “art critics”) and those who employed a checklist approach in their selection process (the “airline captains”).

Those who used the checklist approach had far fewer regrets about their selection of managers, and their investments had higher returns.

But the vast majority of VCs are “art critics,” relying on their instincts and experience, rather than the more successful approach.

In system design, many managers rely on their instincts at the beginning of product development to assess how much staff they’ll need and how long the project will take. Clearly something’s wrong because more than 80 percent of semiconductor projects slip schedule.

Learning from the past

It doesn’t have to be this way. Gawande points out that some in the investment banking community rigorously study past investments to understand where failed investments went awry. Sometimes that education leads to adding a check for their next investment checklist: “read all foot notes in the prospectus,” for example.

Successful system-design teams, whether in name or spirit, use similar approaches, and they start with benchmarking themselves against the industry or their own past efforts to understand how to approach their latest product development.

As Gawande implies, it’s often the simplest approaches—and, I’d add, approaches based on facts rather than instinct—that work most effectively.

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Sometimes the simple questions are the most vexing. That hit me this week while participating in a DesignCon panel in Santa Clara, moderated by EDN Executive Editor Ron Wilson.

The title seemed easy enough: “Getting to Design Quality Closure Without Compromising Productivity.”

But really, what IS quality? How do we define it?

My fellow panelist, Camille Kokozaki, president of Design Rivers, quipped “It’s like pornography: you know it when you see it.”

Piyush Sancheti, senior director of business development at Atrenta, came close:

“Quality is meeting the design objectives you have: whether it’s area, power, timing functionality, or, in a broader sense, customer expectations. Productivity is getting there.”

Sancheti then added:

“Being able to measure it (productivity) with tools like Numetrics is important because you want to hit your objectives as fast and effectively as possible.”

Not surprisingly, our panel wrestled with one of the big issues in design quality today: verification. It deeply affects design quality and productivity. Sancheti noted that for some teams, 70 percent of the entire design development is spent on verification.

What I see first hand from customers is they struggle to understand how verification affects their productivity. Some program managers I talk to say:

“I understand the scope of logic design and physical implementation. Verification is an unknown for me. If I give the verification team another two months, they’ll take it, but how do I know that we’re better off?”

So, I think we’re seeing that verification needs to come up with some sort of model of completion so people can move on. And that’s not easy. Our data shows that some companies toggle up the tape-outs as part of a larger verification strategy, but that can hurt overall productivity.

How we fix verification is a broader issue. Do we lean on formal methods at the architectural level as opposed to time- and engineering-consuming test vectors?

For now, our role is to help teams quantify their design effort, properly staff their projects, and understand where they stand with respect to the industry’s best teams. From there they can make fact-based decisions to drive productivity improvements.

That’s our contribution to the broader challenges of verification and design quality, but as we all know, it takes a village (and many future industry panels) to come up with the solution.

(Jeff is Numetrics’ director of professional services and product marketing).

Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

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