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    Wrestling with Design Quality, Productivity

    by Numetrics | February 5, 2010 | In Best Practices, Productivity | No Comments

    By Jeff Eversmann

    Sometimes the simple questions are the most vexing. That hit me this week while participating in a DesignCon panel in Santa Clara, moderated by EDN Executive Editor Ron Wilson.

    The title seemed easy enough: “Getting to Design Quality Closure Without Compromising Productivity.”

    But really, what IS quality? How do we define it?

    My fellow panelist, Camille Kokozaki, president of Design Rivers, quipped “It’s like pornography: you know it when you see it.”

    Piyush Sancheti, senior director of business development at Atrenta, came close:

    “Quality is meeting the design objectives you have: whether it’s area, power, timing functionality, or, in a broader sense, customer expectations. Productivity is getting there.”

    Sancheti then added:

    “Being able to measure it (productivity) with tools like Numetrics is important because you want to hit your objectives as fast and effectively as possible.”

    Not surprisingly, our panel wrestled with one of the big issues in design quality today: verification. It deeply affects design quality and productivity. Sancheti noted that for some teams, 70 percent of the entire design development is spent on verification.

    What I see first hand from customers is they struggle to understand how verification affects their productivity. Some program managers I talk to say:

    “I understand the scope of logic design and physical implementation. Verification is an unknown for me. If I give the verification team another two months, they’ll take it, but how do I know that we’re better off?”

    So, I think we’re seeing that verification needs to come up with some sort of model of completion so people can move on. And that’s not easy. Our data shows that some companies toggle up the tape-outs as part of a larger verification strategy, but that can hurt overall productivity.

    How we fix verification is a broader issue. Do we lean on formal methods at the architectural level as opposed to time- and engineering-consuming test vectors?

    For now, our role is to help teams quantify their design effort, properly staff their projects, and understand where they stand with respect to the industry’s best teams. From there they can make fact-based decisions to drive productivity improvements.

    That’s our contribution to the broader challenges of verification and design quality, but as we all know, it takes a village (and many future industry panels) to come up with the solution.

    (Jeff is Numetrics’ director of professional services and product marketing).

    Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

    Bright lights in a dimly lit DesignCon room: (L-R) Camille Kokozaki, Design Rivers; Piyush Sancheti, Atrenta; Jeff Eversmann, Numetrics; Michel Tabusse, Satin IP

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    Tagged as: Atrenta, Design Rivers, DesignCon2010, fact-based planning, IC development productivity, product development, Productivity, Risk Analysis, Ron Wilson, Satin IP, Schedule Predictability, semiconductor design, SOC, system-on-chip

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