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    Overcoming the challenges of design reuse: A Webinar

    by Numetrics | January 15, 2010 | In Best Practices, News, Schedule Predictability | 2 Comments

    By Ron Collett

    In December, we were honored to participate in a Design & Reuse panel in Grenoble, France, titled “IP Reuse vs. IP Leverage: What’s the difference and what are the issues?”

    Andrea Fortunato, our European director of professional services, represented us and gave an overview of the particular challenges that design reuse brings. He blogged about it right after the panel (Design Reuse: It’s Harder Than it Looks).

    Our friends at D&R have just posted an audio Webinar of that panel. It’s definitely worth a listen if you’re designing with cores and trying to take advantage of reusability.

    Have you had design reuse challenges recently? If so, feel free to comment on this post to let us know what they were and how you overcame them. Improving productivity in the semiconductor industry is a communal effort!

    Design and Reuse IP Panel Webinar

    Related posts:

    1. The Realities of IP Reuse Long touted as a silver bullet, IP reuse often...

    Related posts brought to you by Yet Another Related Posts Plugin.

    Tagged as: cores, Design and Reuse, design reuse, EDA, ip, ip cores, Jasper Design Automation, Kathryn Kranen, Olivier Haller, Paul Dempsey, Productivity, risk assessment, semiconductor design, software design, STMicroelectronics

    2 Responses »

    1. Numetrics (Numetrics) on January 15, 2010 at 11:41 pm:

      Twitter Comment


      Design & Reuse has posted a Webinar of its Dec. IP design reuse panel (http://bit.ly/75nTdM) We add some context: [link to post] #eda

      – Posted using Chat Catcher

    2. Numetrics (Numetrics) on January 20, 2010 at 8:09 pm:

      Twitter Comment


      Lunch break: Get the inside scoop on design and reuse techniques from a great D&R Webinar [link to post] #semiconductors #eda

      – Posted using Chat Catcher

    Leave a Reply

     
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