(Summary: A clever YouTube video highlights how communications disconnects can prompt IC product-development projects to slip schedule).

By Ron Collett

We talk a lot about schedule predictability and maximizing IC design throughput. That’s what we do as part of our goal to help product-development teams improve productivity and ROI. But there’s another, more subtle goal, and that’s improving engineering communications and expectations.

Engineers will work most productively when given an aggressive schedule if they know it to be realistic because it’s rooted in fact-based planning. With unrealistic schedule assumptions, the reaction is “been there, done that,” and productivity—and ultimately morale—suffers.

This dynamic is vibrantly illustrated in a YouTube video inspired and narrated by Jasper Design Automation CEO Kathryn Kranen, called How Engineers Communicate: A Video Parody.

In it, the mythical company WonderChips is planning its T-1000 communications device. The video takes us through the planning process, the assumptions and most importantly the communications disconnects engineers and executives encounter along the way.

To summarize the story line:

• In the beginning, Rakesh determines that the T-1000 device is four times more complex than its predecessor and therefore a new EDA tool is needed to speed this project to completion on schedule. His boss, however, rejects the investment.

• Next, the T-1000 team grabs a conference room to begin its bottom-up planning approach, fueled by chips and soda and catered food. Hours go by, punctuated by arguments over how long certain blocks will take to design.

• Eventually, the team leader seems satisfied. She tells the group, “Assuming all these assumptions hold, I think the schedule looks really good.” The team agrees, and the leader goes off to present the schedule to executive management.

• Later, she returns to the team with good news and bad news: The good news is the executive staff loves the feature set. Bad news is the T-800, another project, is slipping schedule, and there’s competitive pressure in the market. So the executives want the T-1000 to sample months sooner than the team’s bottom-up plan called for. Oh, and they need to beef up the memory subsystem while they’re at it.

Says the team leader: “I know as a team we can do this. You guys with me?”

The team groans. As the engineers exit the conference room, shaking their heads in disbelief, one engineer murmurs: “It will be done when it is done.”

The T-1000 ends up slipping by at more than six months, and the executive who turned down the tool investment demands tape out at any cost.

From my perspective, WonderChips would have benefited by complementing its bottom-up scheduling approach with a top-down methodology—using quantified estimates of the chip’s complexity, the team’s productivity and a model of the rate at which effort will be expended on the project.

It would have helped engineers and management communicate in a common language and build an aggressive yet achievable schedule. And it would saved WonderChips’ management from having to extend the on-site day care closing time to midnight to get the chip done.

(Summary: More than 80 percent of semiconductor projects slip schedule, but we can change this costly reality by introducing a fact-based planning methodology into semiconductor product-development organizations).

By Ron Collett

The increase in semiconductor design complexity never slows. This reality always reinforces itself when I look at the agenda of a given week’s technology event. This week’s headliner is ARM Techcon3 in Santa Clara.

Here’s a sampling of the presentations:

• “How Software and Hardware Can Cooperate To Manage Power Consumption in ARM-based Systems”
• “Fireside Chat: Enabling Internet Eveywhere and Advancing Next-Generation Designs”
• “Energy Efficient Design at 65nm – What Really Works!”

And the list goes on—challenging design issues at complex technology nodes everywhere you look. It’s little wonder then that most semiconductor design projects slip schedule (see chart).

Old habits in a mature industry die hard. Engineers have built products in more or less the same way for 40 years, and they’ve had tremendous market success. So why change? Engineering intuition always seems to work, and a bottom-up approach to project staffing is the way we’ve always done things. No reason to change, right?

Wrong.

Projects slip for a number of reasons:

• We’re human. Who can predict when or if a spec change might occur or the flu takes out a few key engineers for a week?
• We often lack the context to make fact-based decisions for dizzingly complex designs. For example, if you’ve spread a design over three locations in different time zones, using a newly-acquired team designing to a new process, you’re trying to extrapolate the effect of those factors based on your experience. But you probably have never experienced those factors before because each design is different.
• Projects are late often because they are under-scoped. The schedule for the new project is based largely on the post-mortem of the last project, with the conclusion that none of the things that went wrong last time will be allowed to go wrong this time (and no other major new challenges will be allowed to creep in!).

Typical bottom-up reactions to managing such complexity tend to fall into two categories:

• Boost staff to hit schedule. This generally creates either a low-productivity, low-throughput situation or a high-throughput, low-productivity environment. Teams might hit schedule but will blow out the budget.
• Leverage a small, skilled team of engineers and drive it hard. This can marshal costs and improve decision-making, but a small team can produce only so much in a given period of time, even if it’s highly productive. Too much pressure to hit an unrealistic schedule also kills morale.

Sharp engineering managers can achieve best in class and cut or eliminate schedule slip by adopting a top-down approach that complements their traditional bottom-up planning. The top-down methodology uses:

• Quantified estimates of the chip’s complexity
• The team’s productivity
• A model of the rate at which effort will be expended on the project.

With the proper infrastructure in place, schedule estimates can be generated within just a few hours. At this point you can benchmark against your own experience or against the industry’s experience and make fact-based what-if tradeoffs to boost your schedule predictability and design ROI.

More than 80 percent of semiconductor projects slip schedule. But we can change this reality. You wouldn’t expect this from your foundry, would you? Your foundry partner gives you a precise estimate of yield on your chip based on its models and its vast experiences with similar projects. You should expect the same predictability from your product-development organization.

(Summary: Semiconductor companies are rethinking what it means to be fabless and looking for new ways to differentiate themselves).

By Ron Collett

For the semiconductor industry, there not only is change in the air, there’s thoughtful debate about just what that change looks like.

I’ve been mulling over a couple of intriguing posts, one by another newly minted industry blogger, Sanjay Srivastava, CEO of Denali, and the other on EDN by Kaben Wireless Silicon CEO Paul Slaby.

In Sanjay’s blog, Conversation on Innovation, he’s been mulling how fabless semiconductor startups can survive in the current climate.

He argues (in Funding Fabless Semiconductor Startups) that solutions need to look at how and where money is invested, how we “stage” investments (i.e. valuing investments in IP differently than in silicon) and how we address software investment:

I believe if we get creative about the current fabless investment model, not every semiconductor opportunity needs to be a billion-dollar opportunity before it can attract meaningful investment.

In his EDN post and in a separate webcast, Slaby argues for a “semi-fabless” model:

The semi-fabless company is essentially a combination of an IP provider, a design house, and an outsourced R&D operation. Its core competence and strength lies in specialized R&D and product development capabilities whereas it outsources product delivery operations to the ‘old’ fabless company with the entire infrastructure and the pipeline to market already in place.

There’s no doubt the investment formula needs to be reconsidered. For a semiconductor company to break even, it needs $40-$100 million and six to eight years. More troubling, however, is the selling price of semiconductor startups has been steadily declining. In 2007 it was $160 million; in 2008 it was $95 million and in 2009 the average has been $65 million, according to an EE Times story referencing Lip-Bu Tan, chairman of Walden International, and now CEO of Cadence.

The good thing is there are a lot of “smartest guys in the room” in this industry, and collectively we’re shaping the industry’s future in three main ways:

• Companies are differentiating on products

• Executives, such as Sanjay and Paul and others, are helping drive the investment conversation

• And companies like ours are illuminating the differentiation and benefits of focusing on product-development productivity—fabless companies’ key differentiator today—and overall portfolio management.

This new differentiation is key; it’s key to how companies grow and gain market share and it’s key to the industry’s future.

(Summary: For semiconductor companies, differentiation has shifted from manufacturing to improving productivity in new-product development. That realization is the easy part; getting there requires help.)

By Ron Collett

I’m always impressed with the level of optimism I find at semiconductor industry events around the world. There may be pockets of gloom about the state of the semiconductor industry, but executives certainly don’t share it. Yes, it’s not the same industry it was 10 years ago, but, no, it’s not doomed. Far from it: The dynamics are just different.

That was my message when I presented last week at Malcolm Penn’s International Electronics Forum in Geneva. Here’s why the dynamics are different:

• The industry head count has shrunk 30 percent this decade
• Industry consolidation has picked up pace
• Cost-cutting is rampant
• There’s more pressure than ever on design teams to get great products out the door on time and on budget

Here’s how the dynamics are different: Differentiation has shifted as industry disaggregation has reached an end state. There was a time when a semiconductor company differentiated itself through manufacturing and process technology (or way back when, through making its own steppers!) No longer.

So where’s the differentiation? It’s not in cost-cutting. Everyone’s doing that.

Differentiation has shifted to the heart of the semiconductor company’s value proposition: its new-product development.

Electronics Weekly’s David Manners, in his coverage of IEF last week (“What’s the Answers to the Chip Industry’s Problems? Ask IEF”), touched on how profound this can be. He quoted Alain Dutheil, CEO of ST-Ericsson, as saying 85 percent of his 8,000 employees are in R&D.

The other part of the story, which we’ve blogged about, is that most SOC projects slip schedule and most IC teams tend to underestimate their product R&D costs.

That brings me back to our IEF presentation (“Raising the Bar on Semiconductor R&D Management, Execution, and ROI”), which we created in partnership with PRTM, one of the world’s premier operational strategy consulting firms (with deep ties to the IC industry).

Our three take-aways were:

• The bar is being significantly raised on semiconductor R&D management, execution, and achieving ROI
• Companies must continuously progress through the stages of maturity to thrive (functional, project, portfolio, and cross-enterprise excellence)
• Fact-based planning is a critical foundation for ongoing NPD success

Anyone can cut costs in challenging times but winning companies find news ways to differentiate themselves, and they are the companies that come out of recessions stronger than their competition.