By Ron Collett

I had the pleasure of participating in a great online panel yesterday that was part of the EE Times SOC Virtual Conference, attended live by more than 1,500 people. CTO Grant Martin with Tensilica, product-development Vice President Steve Douglass with Xilinx and ASIC and FPGA designer Sven Andersson of Realtime Embedded AB all contributed to robust discussion of where next-generation design is headed.

I encourage you to listen to panel, which is now archived for the next six months.

My point was pretty straight forward:

• If you misunderstand your semiconductor design project’s true cost, your SOC may be doomed.

Think about it: An SOC design today needs to return 10x its investment. There aren’t a lot of huge end markets that justify SOC projects where the costs and schedule aren’t carefully managed. If the design costs $50 million to $80 million to develop, and there’s only a $200 million market, then the design can’t be justified.

So getting your arms around true development cost is what SOC development is all about.

Related posts:

1. End of the Free Ride According to Pagemill Partners, a well-known Silicon Valley venture capital...

Related posts brought to you by Yet Another Related Posts Plugin.