• The login component features highly-secure protection measures to safeguard your personal information. Your login credentials are transmitted securely using SSL protocol encryption. This is true even though you do not see "https" in the URL, or a lock icon on the bottom of the browser window. If you require additional assistance, please email us at info@numetrics.com

    Numetrics application is temporarily unavailable due to system maintenance.
    Normal operations will be restored by 10:20 PM PST 02-Mar-10.
     
    Enter your personal login to access Numetrics' customer area*
     
       
    * Login name and Passwords are case sensitive
    Forgot your password Security Concerns?
    Don't have a login name? Contact Us
    • Home
    •  
    • Solutions
    •  
    • Products
    •  
    • Services
    •  
    • Consulting
    •  
    • About Us
    •  
    • Library
    • Feedback

    Categories

    • Best Practices
    • Case Studies
    • Customer Testimonials
    • Industry Database
    • News
    • Productivity
    • Products
    • Project Planning
    • Risk Analysis
    • Schedule Predictability

    Recent Articles

    • How productive is your R&D organization?
    • The Brewing Innovation Storm
    • Doing Moore with Less
    • Sleepless in San Jose
    • DVCon and the Design Productivity Crisis
    • Lessons from The Checklist Manifesto

    Archive

    • June 2010
    • May 2010
    • April 2010
    • March 2010
    • February 2010
    • January 2010
    • December 2009
    • November 2009
    • October 2009
    • September 2009
    • August 2009
    • June 2009
    • May 2009
    • April 2009
    • March 2009
    • February 2009
    • January 2009

    Tags

      cores design reuse EDA EE Times ERP software fact-based planning IC development productivity ip ip cores Jasper Design Automation Kathryn Kranen new product development Numetrics Planning planning software product development Productivity project management software Risk Analysis risk assessment risk management Ron Collett Schedule Schedule Predictability semiconductor semiconductor design semiconductors SOC software design system-on-chip

    Blogroll

    • A Conversation on Innovation (Sanjay Srivastava)
    • Daniel Nenni's Silicon Valley Blog
    • EE Times News
    • Harry the ASIC Guy (Harry Gries)
    • Industry Insights (Richard Goering)
    • JB's Circuit (John Blyler)
    • Leibson's Law (Steve Leibson)
    • Low-power Design.com (John Donovan)
    • Practical Chip Design (Ron Wilson)
    • The World is Analog (Mike Demler)

    The Changing Nature of Semiconductor Design

    by Numetrics | September 14, 2009 | In Best Practices | No Comments

    By Ron Collett

    Big changes are occurring before our eyes in the semiconductor world. And while you might say that the industry always has been in a state of flux, understanding the nature of today’s changes is key; reacting properly to that understanding is imperative.

    What’s new? In short, it’s a shift in focus: The long transition toward the fabless model is almost complete. With the numbers of semiconductor companies doing their own manufacturing dwindling to a handful, the time has come for executives and engineering managers to figure out where their differentiation now lies within their companies.

    Manufacturing used to be one of those differentiators. But today, with everyone buying manufacturing services from TSMC, UMC, Chartered or other foundries, there’s very little differentiation in how ICs are manufactured. But there can be enormous differentiation and value in how they’re designed.

    How is this possible, in a world of well-established design-automation tools and methodologies? One approach is to bring more predictability and productivity to design projects and teams; to help engineering managers get insightful, relevant data early in the design decision-making process; and to enable a portfolio of designs to be centrally managed efficiently. That’s our business, and it’s a topic I’ll explore in detail this Wednesday (Sept. 16) during EE Times’ SoC Virtual Conference.

    I’ll be presenting on a panel (Economics of Next-Generation SOC Design: A Node Too Far? 2-3 p.m. PDT) with Grant Martin, chief scientist, Tensilica; Steve Douglass, vice president, product development, Xilinx; and Sven Andersson, ASIC FPGA designer, Realtime Embedded AB. The panel will be moderated by EE Times’ Online Editor Dylan McGrath.

    If you want a peek at some of what will inform my presentation, take a look at our Numetrics solutions page for starters. And then think about the implications of these two statistics:

    * 60 percent of IC projects slip at least one quarter.

    * 16 percent of IC projects slip more than one year.

    I hope to see you live Wednesday during the virtual panel!

    Related posts:

    1. For Semiconductor Companies, a New Focus on Differentiation (Summary: For semiconductor companies, differentiation has shifted from manufacturing...
    2. Why Most Semiconductor Design Projects Slip Schedule (Summary: More than 80 percent of semiconductor projects slip schedule,...
    3. Re-Planning semiconductor design projects effectively Summary: Re-planning a semiconductor design project is often inevitable...
    4. IC Teams Tend to Underestimate SOC Development Costs By Ron Collett Underestimating the complexity of an SOC semiconductor...
    5. Reconsidering the Fabless Semiconductor Model (Summary: Semiconductor companies are rethinking what it means to be...

    Related posts brought to you by Yet Another Related Posts Plugin.

    Tagged as: EE Times, Risk Analysis, risk assessment, risk management, semiconductor design, semiconductors, SOC, system-on-chip

    Leave a Reply

     
  • Copyright © 2010 Numetrics Management Systems, Inc. All rights reserved