By Ron Collett

Underestimating the complexity of an SOC semiconductor design project is a growing problem in our industry. In an era where SOC projects cost tens of millions of dollars to complete, a week of schedule slip means $1 million or more in lost revenue potential. That’s unacceptable.

That was my main point last week during a panel I participated on that was part of the EE Times SOC Virtual Conference.

Former EE Times EDA Editor Richard Goering, now blogging for Cadence, captured the panel well in a post this week (Are SoC Development Costs Significantly Underestimated?).

To justify the investment in an SoC, Collett said, the available revenue stream must be 10X the development costs. Thus, if an SoC has a $500 million market opportunity, development costs should not exceed $50 million. Today, however, development costs can easily reach $40 to $80 million. Collett noted that 60 percent of this cost is labor and that the major part of the overall development cost is verification.

Richard, with a great comparison, went on to write:

Anyone who has ever been involved in a home remodeling project knows how hard it is to get a reliable estimate up front of how long it will take and how much it will cost. Underestimating time and cost is commonplace. A large SoC design project is far more complex, with many more stakeholders. There is no simple answer to the question of how development costs can be accurately predicted. But there are some ideas about how to lower development costs.

Tensilica CTO Grant Martin weighed in from the IP perspective, Xilinx VP of Product Development Steve Douglass offered the FPGA perspective, and ASIC designer Sven Andersson from Realtime Embedded AB talked about the value of verified IP blocks. It was a great conversation, and you can hear it in archived form by registering for the event.

There’s some additional information about the panel (we tweeted some highlights during the panel) that have been cataloged under the hash tag #eetsoc.And we’ve published a helpful white paper on how to measure IC development productivity in our online library.

Time really is money in the semiconductor industry, and quantifying schedule risk is an excellent way to maximize your engineering investments.

By Ron Collett

I had the pleasure of participating in a great online panel yesterday that was part of the EE Times SOC Virtual Conference, attended live by more than 1,500 people. CTO Grant Martin with Tensilica, product-development Vice President Steve Douglass with Xilinx and ASIC and FPGA designer Sven Andersson of Realtime Embedded AB all contributed to robust discussion of where next-generation design is headed.

I encourage you to listen to panel, which is now archived for the next six months.

My point was pretty straight forward:

• If you misunderstand your semiconductor design project’s true cost, your SOC may be doomed.

Think about it: An SOC design today needs to return 10x its investment. There aren’t a lot of huge end markets that justify SOC projects where the costs and schedule aren’t carefully managed. If the design costs $50 million to $80 million to develop, and there’s only a $200 million market, then the design can’t be justified.

So getting your arms around true development cost is what SOC development is all about.

By Ron Collett

Big changes are occurring before our eyes in the semiconductor world. And while you might say that the industry always has been in a state of flux, understanding the nature of today’s changes is key; reacting properly to that understanding is imperative.

What’s new? In short, it’s a shift in focus: The long transition toward the fabless model is almost complete. With the numbers of semiconductor companies doing their own manufacturing dwindling to a handful, the time has come for executives and engineering managers to figure out where their differentiation now lies within their companies.

Manufacturing used to be one of those differentiators. But today, with everyone buying manufacturing services from TSMC, UMC, Chartered or other foundries, there’s very little differentiation in how ICs are manufactured. But there can be enormous differentiation and value in how they’re designed.

How is this possible, in a world of well-established design-automation tools and methodologies? One approach is to bring more predictability and productivity to design projects and teams; to help engineering managers get insightful, relevant data early in the design decision-making process; and to enable a portfolio of designs to be centrally managed efficiently. That’s our business, and it’s a topic I’ll explore in detail this Wednesday (Sept. 16) during EE Times’ SoC Virtual Conference.

I’ll be presenting on a panel (Economics of Next-Generation SOC Design: A Node Too Far? 2-3 p.m. PDT) with Grant Martin, chief scientist, Tensilica; Steve Douglass, vice president, product development, Xilinx; and Sven Andersson, ASIC FPGA designer, Realtime Embedded AB. The panel will be moderated by EE Times’ Online Editor Dylan McGrath.

If you want a peek at some of what will inform my presentation, take a look at our Numetrics solutions page for starters. And then think about the implications of these two statistics:

* 60 percent of IC projects slip at least one quarter.

* 16 percent of IC projects slip more than one year.

I hope to see you live Wednesday during the virtual panel!